Texas Instruments SM320F2812-HT Data Data Manual Download

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SPICTL.0

SPI INT FLAG

SPI INT

ENA

SPISTS.6

Clock

Polarity

Talk

LSPCLK

SPI Bit Rate

State Control

SPIRXBUF

Buffer Register

Clock

Phase

Receiver

Overrun Flag

SPICTL.4

Overrun

INT ENA

SPICCR.3 − 0

SPIBRR.6 − 0

SPICCR.6

SPICTL.3

SPIDAT.15 − 0

SPICTL.1

Master/Slave

SPISTS.7

SPIDAT

Data Register

SPICTL.2

SPI Char

SPISIMO

SPISOMI

SPICLK

SW2

SW3

To CPU

SW1

SPITXBUF

Buffer Register

RX FIFO _0
RX FIFO _1

−−−−−

RX FIFO _15

TX FIFO registers

TX FIFO _0

TX FIFO _1

−−−−−

TX FIFO _15

RX FIFO registers

TX Interrupt

Logic

RX Interrupt

Logic

SPIINT/SPIRXINT

SPITXINT

SPIFFOVF FLAG

SPIFFRX.15

TX FIFO Interrupt

RX FIFO Interrupt

SPIRXBUF

SPITXBUF

SPIFFTX.14

SPIFFENA

SPISTE

†

SPISTE is driven low by the master for a slave device.

SM320F2812-HT

SGUS062B

–

JUNE 2009

–

REVISED JUNE 2011

www.ti.com

Figure 4-11

is a block diagram of the SPI in slave mode.

Figure 4-11. Serial Peripheral Interface Module Block Diagram (Slave Mode)

Peripherals

2009

–

2011, Texas Instruments Incorporated

Submit Documentation Feedback

Product Folder Link(s):

SM320F2812-HT

Summary of Contents for SM320F2812-HT Data

Page 1: ...information is current as of publication date Products conform to specifications per the terms of the Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters Literature Number SGUS062B June 2009 Revised June 2011 ...

Page 2: ... 32 3 2 11 External Interrupts XINT1 XINT2 XINT13 XNMI 32 3 2 12 Oscillator and PLL 32 3 2 13 Watchdog 32 3 2 14 Peripheral Clocking 32 3 2 15 Low Power Modes 32 3 2 16 Peripheral Frames 0 1 2 PFn 33 3 2 17 General Purpose Input Output GPIO Multiplexer 33 3 2 18 32 Bit CPU Timers 0 1 2 33 3 2 19 Control Peripherals 33 3 2 20 Serial Port Peripherals 34 3 3 Register Map 34 3 4 Device Emulation Regis...

Page 3: ...1 6 Electrical Specifications 84 6 1 Absolute Maximum Ratings 84 6 2 Recommended Operating Conditions 85 6 3 Electrical Characteristics 85 6 4 Current Consumption by Power Supply Pins Over Recommended Operating Conditions During Low Power Modes at 150 MHz SYSCLKOUT 87 6 5 Current Consumption Graphs 88 6 6 Reducing Current Consumption 89 6 7 Power Sequencing Requirements 89 6 8 Signal Transition Le...

Page 4: ...Detailed Description 135 6 29 5 1 Reference Voltage 135 6 29 5 2 Analog Inputs 135 6 29 5 3 Converter 135 6 29 5 4 Conversion Modes 135 6 29 6 Sequential Sampling Mode Single Channel SMODE 0 135 6 29 7 Simultaneous Sampling Mode Dual Channel SMODE 1 137 6 29 8 Definitions of Specifications and Terminology 138 6 29 8 1 Integral Nonlinearity 138 6 29 8 2 Differential Nonlinearity 138 6 29 8 3 Zero O...

Page 5: ...erface SCI Module Block Diagram 73 4 11 Serial Peripheral Interface Module Block Diagram Slave Mode 76 4 12 GPIO Peripheral Pin Multiplexing 79 5 1 28x Device Nomenclature 81 6 1 SM320F2812 HT Life Expectancy Curve 86 6 2 Typical Current Consumption Over Frequency 88 6 3 Typical Power Consumption Over Frequency 89 6 4 F2812 Typical Power Up and Power Down Sequence Option 2 90 6 5 Output Levels 91 ...

Page 6: ...Access 126 6 34 Write With Asynchronous XREADY Access 127 6 35 External Interface Hold Waveform 129 6 36 XHOLD XHOLDA Timing Requirements XCLKOUT 1 2 XTIMCLK 130 6 37 ADC Analog Input Impedance Model 134 6 38 ADC Power Up Control Bit Timing 134 6 39 Sequential Sampling Mode Single Channel Timing 136 6 40 Simultaneous Sampling Mode Timing 137 6 41 McBSP Receive Timing 141 6 42 McBSP Transmit Timing...

Page 7: ...DC Registers 62 4 5 3 3 V eCAN Transceivers for the SM320F2812 DSP 64 4 6 CAN Registers Map 66 4 7 McBSP Register Summary 69 4 8 SCI A Registers 72 4 9 SCI B Registers 72 4 10 SPI Registers 75 4 11 GPIO Mux Registers 77 4 12 GPIO Data Registers 78 6 1 Typical Current Consumption by Various Peripherals at 150 MHz 89 6 2 Recommended Low Dropout Regulators 89 6 3 Clock Table and Nomenclature 93 6 4 I...

Page 8: ...n Read 1 Wait State 122 6 40 Asynchronous XREADY Timing Requirements Ready on Read 1 Wait State 122 6 41 External Memory Interface Write Switching Characteristics Ready on Write 1 Wait State 125 6 42 Synchronous XREADY Timing Requirements Ready on Write 1 Wait State 125 6 43 Asynchronous XREADY Timing Requirements Ready on Write 1 Wait State 125 6 44 XHOLD XHOLDA Timing Requirements XCLKOUT XTIMCL...

Page 9: ...SM320F2812 HT www ti com SGUS062B JUNE 2009 REVISED JUNE 2011 6 65 Minimum Required Wait States at Different Frequencies 147 Copyright 2009 2011 Texas Instruments Incorporated List of Tables 9 ...

Page 11: ... Four Up to 56 Individually Programmable 8K 16 and Six 16K 16 Sectors Multiplexed General Purpose Input Output GPIO Pins ROM Devices Up to 128K 16 ROM Advanced Emulation Features 1K 16 OTP ROM Analysis and Breakpoint Functions L0 and L1 2 Blocks of 4K 16 Each Single Access RAM SARAM Real Time Debug via Hardware H0 1 Block of 8K 16 SARAM Development Tools Include M0 and M1 2 Blocks of 1K 16 Each AN...

Page 12: ... 55 C 220 C Temperature Range 2 Extended Product Life Cycle Extended Product Change Notification Product Traceability Texas Instruments high temperature products utilize highly optimized silicon die solutions with design and process enhancements to maximize performance over extended temperatures 2 Custom temperature ranges available 12 Features Copyright 2009 2011 Texas Instruments Incorporated ...

Page 13: ... 18K 3 3 V On Chip Flash 16 bit word 128K On Chip ROM 16 bit word Code Security for On Chip Flash SARAM OTP ROM Yes Boot ROM Yes OTP ROM 1K 16 Yes External Memory Interface Yes Event Managers A and B EVA and EVB EVA EVB General Purpose GP Timers 4 Compare CMP PWM 16 Capture CAP QEP Channels 6 2 Watchdog Timer Yes 12 Bit ADC Yes Channels 16 32 Bit CPU Timers 3 SPI Yes SCIA SCIB SCIA SCIB CAN Yes Mc...

Page 14: ... Die Layout Table 2 2 Bare Die Information DIE PAD DIE PAD DIE BACKSIDE BACKSIDE DIE SIZE DIE PAD SIZE COMPOSITI COORDINATES THICKNESS FINISH POTENTIAL ON 219 4 x 207 0 mils Silicon with 55 0 x 64 0 μm See Table 2 3 11 0 mils AlCu TiN Ground 5572 0 x 5258 0 μm backgrind 14 Introduction Copyright 2009 2011 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812...

Page 15: ...DIO XD 8 TEST2 TEST1 XD 9 VDD3VFL TDIRB TCLKINB XD 10 XD 11 VDD X2 X1 XCLKIN VSS T3CTRIP_PDPINTB XA 2 VDDIO XHOLDA T4CTRIP EVBSOC XWE XA 3 VSS CANTXA XZCS2 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 ...

Page 16: ... 5057 5 O Z XA 4 101 116 3518 7 5057 5 O Z XA 3 83 96 5361 5 4471 5 O Z XA 2 78 91 5361 5 3927 2 O Z XA 1 42 49 5024 5 42 6 O Z XA 0 18 24 2403 5 42 6 O Z XD 15 144 162 42 6 3306 9 I O Z PU XD 14 136 152 42 6 4277 3 I O Z PU XD 13 95 110 4194 1 5057 5 I O Z PU XD 12 94 109 4318 1 5057 5 I O Z PU XD 11 72 85 5361 5 3382 2 I O Z PU XD 10 71 84 5361 5 3258 3 I O Z PU XD 9 67 77 5361 5 2608 4 I O Z PU...

Page 17: ...ly drive the external bus when XHOLDA is active low XINTF Zone 0 and Zone 1 Chip Select XZCS0AND1 is active low when an XZCS0AND1 43 50 5148 5 42 6 O Z access to the XINTF Zone 0 or Zone 1 is performed XINTF Zone 2 Chip Select XZCS2 is active XZCS2 86 100 5361 5 4844 2 O Z low when an access to the XINTF Zone 2 is performed XINTF Zone 6 and Zone 7 Chip Select XZCS6AND7 is active low when an XZCS6A...

Page 18: ...17 132 1701 2 5057 5 O 1 2 the frequency or 1 4 the frequency of SYSCLKOUT At reset XCLKOUT SYSCLKOUT 4 The XCLKOUT signal can be turned off by setting bit 3 CLKOFF of the XINTCNF2 register to 1 Test Pin Reserved for TI Must be TESTSEL 131 147 42 6 4764 6 I PD connected to ground Device Reset in and Watchdog Reset out Device reset XRS causes the device to terminate execution The PC points to the a...

Page 19: ...ated for proper operation of the debugger and the application TCK 133 149 42 6 4605 1 I PU JTAG test clock with internal pullup JTAG test mode select TMS with internal pullup This serial control input is clocked TMS 123 139 872 5 5057 5 I PU into the TAP controller on the rising edge of TCK JTAG test data input TDI with internal pullup TDI is clocked into the selected TDI 128 144 350 4 5057 5 I PU...

Page 20: ...5 1545 8 42 6 O reference input 2 V if the software bit is enabled for this mode 1 μF to 10 μF low ESR capacitor can be used in the external reference mode ADC Voltage Reference Output 1 V Requires a low ESR 50 mΩ 1 5 Ω ceramic bypass capacitor of 10 μF to analog ground Can accept external ADCREFM 10 14 1450 5 42 6 O reference input 1 V if the software bit is enabled for this mode 1 μF to 10 μF lo...

Page 21: ...5 5361 5 1514 6 VSS 79 5361 5 2818 6 VSS 76 89 5361 5 3754 9 VSS 84 97 5361 5 4585 7 Core and Digital I O Ground Pins VSS 97 112 3956 0 5057 5 VSS 103 118 3280 5 5057 5 VSS 111 126 2357 2 5057 5 VSS 133 1587 1 5057 5 VSS 126 142 569 0 5057 5 VSS 139 155 42 6 3915 2 VSS 159 42 6 3580 8 VSS 168 42 6 2705 4 VDDIO 30 37 3776 0 42 6 VDDIO 63 73 5361 5 2226 0 VDDIO 79 92 5361 5 4051 2 3 3 V I O Digital ...

Page 22: ...I 114 129 2073 2 5057 5 I O Z PU Direction GPIO or Timer Clock GPIOA12 TCLKINA I 115 130 1949 2 5057 5 I O Z PU Input GPIO or Compare 1 GPIOA13 C1TRIP I 119 135 1368 4 5057 5 I O Z PU Output Trip GPIO or Compare 2 GPIOA14 C2TRIP I 120 136 1244 5 5057 5 I O Z PU Output Trip GPIO or Compare 3 GPIOA15 C3TRIP I 121 137 1120 5 5057 5 I O Z PU Output Trip GPIOB OR EVB SIGNALS GPIO or PWM GPIOB0 PWM7 O 4...

Page 23: ...057 5 I O Z PU External ADC Start of Conversion EV A GPIOD OR EVB SIGNALS Timer 3 Compare GPIOD5 T3CTRIP_PDPINTB I 77 90 5361 5 3841 1 I O Z PU Output Trip Timer 4 Compare Output Trip or GPIOD6 T4CTRIP EVBSOC I 81 94 5361 5 4261 4 I O Z PU External ADC Start of Conversion EV B GPIOE OR INTERRUPT SIGNALS GPIO or XINT1 or GPIOE0 XINT1_XBIO I 146 164 42 6 3059 0 I O Z XBIO input GPIO or XINT2 or GPIO...

Page 24: ...2 3 42 6 I O Z serial data GPIO or received GPIOF13 MDRA I 19 26 2613 0 42 6 I O Z PU serial data GPIOF OR XF CPU OUTPUT SIGNAL This pin has three functions 1 XF General purpose output pin 2 XPLLDIS This pin is sampled during reset to check if the PLL needs to GPIOF14 XF_XPLLDIS O 137 153 42 6 4153 3 I O Z PU be disabled The PLL will be disabled if this pin is sensed low HALT and STANDBY modes can...

Page 25: ...hDog FIFO FIFO PIE 96 interrupts RS SPI FIFO TINT0 TINT1 TINT2 Control Address 19 Data 16 External Interface XINTF 16 Channels 45 of the possible 96 interrupts are used on the device GPIO Pins XRS X1 XCLKIN X2 XF_XPLLDIS Protected by the code security module XINT13 G P I O M U X L1 SARAM 4K x 16 XNMI L0 SARAM 4K x 16 SM320F2812 HT www ti com SGUS062B JUNE 2009 REVISED JUNE 2011 3 Functional Overvi...

Page 27: ...timing wait states and to either sample or ignore external ready signal This makes interfacing to external peripherals easy and glueless NOTE The chip selects of XINTF Zone 0 and Zone 1 are merged together into a single chip select XZCS0AND1 and the chip selects of XINTF Zone 6 and Zone 7 are merged together into a single chip select XZCS6AND7 See Section 3 5 External Interface XINTF 2812 only for...

Page 28: ...AMs 0 wait Fixed Peripheral Frame 0 0 wait Fixed 0 wait writes Peripheral Frame 1 Fixed 2 wait reads 0 wait writes Peripheral Frame 2 Fixed 2 wait reads L0 and L1 SARAMs 0 wait Programmable Programmed via the Flash registers 1 wait state operation is possible at a reduced OTP or ROM 1 wait minimum CPU frequency See Section 3 2 6 Flash F281x Only for more information Programmed via the Flash regist...

Page 29: ...bus data read bus and data write bus The program read bus consists of 22 address lines and 32 data lines The data read and write busses consist of 32 address lines and 32 data lines each The 32 bit wide data busses enable single cycle 32 bit operations The multiple bus architecture commonly termed Harvard Bus enables the C28x to fetch an instruction read a data value and write a data value in a si...

Page 30: ...flash module to achieve higher performance The flash OTP is mapped to both program and data space therefore it can be used to execute code or store data information NOTE The F2812 Flash and OTP wait states can be configured by the application This allows applications running at slower frequencies to configure the flash to use fewer wait states Flash effective performance can be improved by enablin...

Page 31: ...ying to boot load some undesirable software that would export the secure memory contents To enable access to the secure blocks the user must write the correct 128 bit KEY value which matches the value stored in the password locations within the Flash ROM NOTE For code security operation all addresses between 0x3F7F80 and 0x3F7FF5 cannot be used as program code or data but must be programmed to 0x0...

Page 32: ...h is reset to zero when a valid interrupt edge is detected This counter can be used to accurately time stamp the interrupt 3 2 12 Oscillator and PLL The F2812 can be clocked by an external oscillator or by a crystal attached to the on chip oscillator circuit A PLL is provided supporting up to 10 input clock scaling ratios The PLL ratios can be changed on the fly in software enabling the user to sc...

Page 33: ...ic inputs the user can also select the number of input qualification cycles This is to filter unwanted noise glitches 3 2 18 32 Bit CPU Timers 0 1 2 CPU Timers 0 1 and 2 are identical 32 bit timers with presettable periods and with 16 bit clock prescaling The timers have a 32 bit count down register which generates an interrupt when the counter reaches zero The counter is decremented at the CPU cl...

Page 34: ...nal peripherals or another processor Typical applications include external I O or peripheral expansion through devices such as shift registers display drivers and ADCs Multi device communications are supported by the master slave operation of the SPI On the F2812 the port supports a 16 level receive and transmit FIFO for reducing servicing overhead SCI The serial communications interface is a two ...

Page 35: ...0 0FFF 1 Registers in Frame 0 support 16 bit and 32 bit accesses 2 If registers are EALLOW protected then writes cannot be performed until the user executes the EALLOW instruction The EDIS instruction disables writes This prevents stray code or pointers from corrupting register contents 3 The Flash Registers are also protected by the Code Security Module CSM Table 3 5 Peripheral Frame 1 Registers ...

Page 36: ... 0x00 70E0 GPIO Data Registers 32 Not EALLOW Protected 0x00 70FF 0x00 7100 ADC Registers 32 Not EALLOW Protected 0x00 711F 0x00 7120 reserved 736 0x00 73FF 0x00 7400 EV A Registers 64 Not EALLOW Protected 0x00 743F 0x00 7440 reserved 192 0x00 74FF 0x00 7500 EV B Registers 64 Not EALLOW Protected 0x00 753F 0x00 7540 reserved 528 0x00 774F 0x00 7750 SCI B Registers 16 Not EALLOW Protected 0x00 775F ...

Page 37: ...D Register 0x0004 Reserved Device ID Register 0x0005 Silicon Rev E PROTSTART 0x00 0884 1 Block Protection Start Address Register PROTRANGE 0x00 0885 1 Block Protection Range Address Register 0x00 0886 reserved 378 0x00 09FF 3 5 External Interface XINTF This section gives a top level view of the external interface XINTF that is implemented on the F2812 device The external interface is a non multipl...

Page 38: ...ip selects XZCS0AND1 XZCS2 XZCS6AND7 which toggle when an access to a particular zone is performed These features enable glueless connection to many external memories and peripherals C The chip selects for Zone 0 and 1 are ANDed internally together to form one chip select XZCS0AND1 Any external memory that is connected to XZCS0AND1 is dually mapped to both Zones 0 and Zone 1 D The chip selects for...

Page 39: ... Registers XINTF signal timing can be tuned to match specific external device requirements such as setup and hold times to strobe signals for contention avoidance and maximizing bus efficiency The timing parameters can be configured individually for each zone This allows the programmer to maximize the efficiency of the bus based on the type of memory or peripheral that the user needs to access All...

Page 40: ...le 96 interrupts 45 are currently used by peripherals SM320F2812 HT SGUS062B JUNE 2009 REVISED JUNE 2011 www ti com 3 6 Interrupts Figure 3 4 shows how the various interrupt sources are multiplexed within the F2812 device Figure 3 4 Interrupt Sources Eight PIE block interrupts are grouped into one CPU interrupt In total 12 CPU interrupt groups with 8 interrupts per group equals 96 possible interru...

Page 41: ...V B EV B EV B CAPINT6 CAPINT5 CAPINT4 T4OFINT T4UFINT T4CINT T4PINT INT5 reserved EV B EV B EV B EV B EV B EV B EV B MXINT MRINT SPITXINTA SPIRXINTA INT6 reserved reserved reserved reserved McBSP McBSP SPI SPI INT7 reserved reserved reserved reserved reserved reserved reserved reserved INT8 reserved reserved reserved reserved reserved reserved reserved reserved ECAN1INT ECAN0INT SCITXINTB SCIRXINT...

Page 42: ...able Register PIEIFR6 0x0000 0CED 1 PIE INT6 Group Flag Register PIEIER7 0x0000 0CEE 1 PIE INT7 Group Enable Register PIEIFR7 0x0000 0CEF 1 PIE INT7 Group Flag Register PIEIER8 0x0000 0CF0 1 PIE INT8 Group Enable Register PIEIFR8 0x0000 0CF1 1 PIE INT8 Group Flag Register PIEIER9 0x0000 0CF2 1 PIE INT9 Group Enable Register PIEIFR9 0x0000 0CF3 1 PIE INT9 Group Flag Register PIEIER10 0x0000 0CF4 1 ...

Page 43: ...trol register XINT1CTR 0x00 7078 1 XINT1 counter register XINT2CTR 0x00 7079 1 XINT2 counter register 0x00 707A reserved 5 0x00 707E XNMICTR 0x00 707F 1 XNMI counter register Each external interrupt can be enabled disabled or qualified using positive or negative going edge For more information see the TMS320x281x System Control and Interrupts Reference Guide SPRU078 Copyright 2009 2011 Texas Instr...

Page 44: ...e low power modes Figure 3 6 shows the various clock and reset domains in the F2812 device that are discussed A CLKIN is the clock input to the CPU SYSCLKOUT is the output clock of the CPU They are of the same frequency Figure 3 6 Clock and Reset Domains 44 Functional Overview Copyright 2009 2011 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT ...

Page 45: ...1 Low Power Mode Control Register 0 LPMCR1 0x00 701F 1 Low Power Mode Control Register 1 reserved 0x00 7020 1 PLLCR 0x00 7021 1 PLL Control Register 2 SCSR 0x00 7022 1 System Control Status Register WDCNTR 0x00 7023 1 Watchdog Counter Register reserved 0x00 7024 1 WDKEY 0x00 7025 1 Watchdog Reset Key Register 0x00 7026 reserved 3 0x00 7028 WDCR 0x00 7029 1 Watchdog Control Register 0x00 702A reser...

Page 46: ...d not exceed VDD The PLLCR bits 3 0 set the clocking ratio Table 3 14 PLLCR Register Bit Definitions BIT S NAME TYPE XRS RESET 1 DESCRIPTION 15 04 reserved R 0 0 00 SYSCLKOUT XCLKIN x n 2 where n is the PLL multiplication factor Bit Value n SYSCLKOUT 0000 PLL Bypassed XCLKIN 2 0001 1 XCLKIN 2 0010 2 XCLKIN 0011 3 XCLKIN 1 5 0100 4 XCLKIN 2 0101 5 XCLKIN 2 5 0110 6 XCLKIN 3 3 00 DIV R W 0 0 0 0 011...

Page 47: ... an external crystal resonator to provide the time base to the device External clock source operation This mode allows the internal oscillator to be bypassed The device clocks are generated from an external clock source input on the X1 XCLKIN pin A TI recommends that customers have the resonator crystal vendor characterize the operation of their device with the DSP chip The resonator crystal vendo...

Page 48: ...y register which resets the watchdog counter Figure 3 9 shows the various functional blocks within the watchdog module A The WDRST signal is driven low for 512 OSCCLK cycles Figure 3 9 Watchdog Module The WDINT signal enables the watchdog to be used as a wakeup from IDLE STANDBY mode timer In STANDBY mode all peripherals are turned off on the device The only peripheral that remains functional is t...

Page 49: ...the 24x 240x the clock is turned off 3 On the C28x the JTAG port can still function even if the core clock CLKIN is turned off 4 On the C28x the JTAG port can still function even if the core clock CLKIN is turned off The various low power modes operate as follows IDLE Mode This mode is exited by any enabled interrupt or an XNMI that is recognized by the processor The LPM block performs no tasks du...

Page 50: ...al port McBSP module Serial communications interface modules SCI A SCI B Serial peripheral interface SPI module Digital I O and shared pin functions 4 1 32 Bit CPU Timers 0 1 2 There are three 32 bit CPU timers on the F2812 devices CPU TIMER0 1 2 CPU Timers 1 and 2 are reserved for the real time OS such as DSP BIOS CPU Timer 0 can be used in user applications These timers are different from the ge...

Page 51: ...or clock Figure 4 2 CPU Timer Interrupts Signals and Output Signal See Notes A and B The general operation of the timer is as follows The 32 bit counter register TIMH TIM is loaded with the value in the period register PRDH PRD The counter register decrements at the SYSCLKOUT rate of the C28x When the counter reaches 0 a timer interrupt output signal generates an interrupt pulse The registers list...

Page 52: ...er High TIMER1PRD 0x00 0C0A 1 CPU Timer 1 Period Register TIMER1PRDH 0x00 0C0B 1 CPU Timer 1 Period Register High TIMER1TCR 0x00 0C0C 1 CPU Timer 1 Control Register reserved 0x00 0C0D 1 TIMER1TPR 0x00 0C0E 1 CPU Timer 1 Prescale Register TIMER1TPRH 0x00 0C0F 1 CPU Timer 1 Prescale Register High TIMER2TIM 0x00 0C10 1 CPU Timer 2 Counter Register TIMER2TIMH 0x00 0C11 1 CPU Timer 2 Counter Register H...

Page 53: ...r more information see the TMS320x281x DSP Event Manager EV Reference Guide SPRU065 Table 4 2 Module and Signal Names for EVA and EVB EVA EVB EVENT MANAGER MODULES MODULE SIGNAL MODULE SIGNAL GP Timer 1 T1PWM T1CMP GP Timer 3 T3PWM T3CMP GP Timers GP Timer 2 T2PWM T2CMP GP Timer 4 T4PWM T4CMP Compare 1 PWM1 2 Compare 4 PWM7 8 Compare Units Compare 2 PWM3 4 Compare 5 PWM9 10 Compare 3 PWM5 6 Compar...

Page 54: ...Control Register A CAPFIFOA 0x00 7422 1 Capture FIFO Status Register A CAP1FIFO 0x00 7423 1 Two Level Deep Capture FIFO Stack 1 CAP2FIFO 0x00 7424 1 Two Level Deep Capture FIFO Stack 2 CAP3FIFO 0x00 7425 1 Two Level Deep Capture FIFO Stack 3 CAP1FBOT 0x00 7427 1 Bottom Register Of Capture FIFO Stack 1 CAP2FBOT 0x00 7428 1 Bottom Register Of Capture FIFO Stack 2 CAP3FBOT 0x00 7429 1 Bottom Register...

Page 55: ...2CMP GPTCONA 3 2 T2CON 1 T2CON 15 11 7 6 3 2 0 ACTRA 15 12 COMCONA 12 T1CON 13 11 CAPCONA 10 9 16 DBTCONA 15 0 ACTRA 11 0 TCLKINA Prescaler HSPCLK T2CON 10 8 T2CON 5 4 clock dir CAPCONA 15 12 7 0 CAP1_QEP1 CAP2_QEP2 CAP3_QEPI1 QEP Logic QEPCLK QEPDIR 16 16 reset EVAENCLK Control Logic Peripheral Bus TDIRA Index Qual EXTCONA 1 2 16 EVASOC ADC External SM320F2812 HT www ti com SGUS062B JUNE 2009 REV...

Page 56: ... programmable deadband circuit The state of each of the six outputs is configured independently The compare registers of the compare units are double buffered allowing programmable change of the compare PWM pulse widths as needed 4 2 3 Programmable Deadband Generator Deadband generation can be enabled disabled for each compare unit output individually The deadband generator circuit produces two ou...

Page 57: ...CAPFIFOx Selection of GP timer 1 2 for EVA or 3 4 for EVB as the time base Three 16 bit 2 level deep FIFO stacks one for each capture unit Three capture input pins CAP1 2 3 for EVA CAP4 5 6 for EVB one input pin per capture unit All inputs are synchronized with the device CPU clock In order for a transition to be captured the input must hold at its current level to meet the input qualification cir...

Page 58: ...equencer can operate in start stop mode allowing multiple time sequenced triggers to synchronize conversions EVA and EVB triggers can operate independently in dual sequencer mode Sample and hold S H acquisition time window has separate prescale control The ADC module in the F2812 has been enhanced to provide flexible interface to event managers A and B The ADC interface is built around a fast 12 b...

Page 59: ...re accessed at the SYSCLKOUT rate The internal timing of the ADC module is controlled by the high speed peripheral clock HSPCLK 2 The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as follows ADCENCLK On reset this signal is low While reset is active low XRS the clock to the register still functions This is necessary to make sure all registers and modes go into t...

Page 60: ...log Inputs Provide access to this pin in PCB layouts Intended for test purposes only TAIYO YUDEN EMK325F106ZH EMK325BJ106MD or equivalent NOTES A External decoupling capacitors are recommended on all power pins B Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance C Use 24 9 kΩ for ADC clock range 1 18 75 MHz use 20 kΩ for ADC clock range 18 75 25 M...

Page 61: ...tional amplifier that does not degrade the ADC performance C Use 24 9 kΩ for ADC clock range 1 18 75 MHz use 20 kΩ for ADC clock range 18 75 25 MHz D It is recommended that buffered external references be provided with a voltage difference of ADCREFP ADCREFM 1 V 0 1 or better External reference is enabled using bit 8 in the ADCTRL3 Register at ADC power up In this mode the accuracy of external ref...

Page 62: ...0x00 710B 1 ADC Conversion Result Buffer Register 3 ADCRESULT4 0x00 710C 1 ADC Conversion Result Buffer Register 4 ADCRESULT5 0x00 710D 1 ADC Conversion Result Buffer Register 5 ADCRESULT6 0x00 710E 1 ADC Conversion Result Buffer Register 6 ADCRESULT7 0x00 710F 1 ADC Conversion Result Buffer Register 7 ADCRESULT8 0x00 7110 1 ADC Conversion Result Buffer Register 8 ADCRESULT9 0x00 7111 1 ADC Conver...

Page 63: ...t scheme with two interrupt levels Employs a programmable alarm on transmission or reception time out Low power mode Programmable wake up on bus activity Automatic reply to a remote request message Automatic retransmission of a frame in case of loss of arbitration or error 32 bit local network time counter synchronized by a specific message communication in conjunction with mailbox 16 Self test mo...

Page 64: ... 3 V eCAN Transceivers for the SM320F2812 DSP SUPPLY LOW POWER SLOPE PART NUMBER VREF OTHER TA VOLTAGE MODE CONTROL SN65HVD230 3 3 V Standby Adjustable Yes 40 C to 85 C SN65HVD230Q 3 3 V Standby Adjustable Yes 40 C to 125 C SN65HVD231 3 3 V Sleep Adjustable Yes 40 C to 85 C SN65HVD231Q 3 3 V Sleep Adjustable Yes 40 C to 125 C SN65HVD232 3 3 V None None None 40 C to 85 C SN65HVD232Q 3 3 V None None...

Page 65: ...Time Out Status CANTOS Reserved eCAN Control and Status Registers Message Identifier MSGID 61E8h 61E9h Message Control MSGCTRL Message Data Low MDL Message Data High MDH Message Mailbox 16 Bytes Control and Status Registers 6000h 603Fh Local Acceptance Masks LAM 32 32 Bit RAM 6040h 607Fh 6080h 60BFh 60C0h 60FFh eCAN Memory 512 Bytes Message Object Time Stamps MOTS 32 32 Bit RAM Message Object Time...

Page 66: ...010 1 Remote frame pending CANGAM 0x00 6012 1 Global acceptance mask CANMC 0x00 6014 1 Master control CANBTC 0x00 6016 1 Bit timing configuration CANES 0x00 6018 1 Error and status CANTEC 0x00 601A 1 Transmit error counter CANREC 0x00 601C 1 Receive error counter CANGIF0 0x00 601E 1 Global interrupt flag 0 CANGIM 0x00 6020 1 Global interrupt mask CANGIF1 0x00 6022 1 Global interrupt flag 1 CANMIM ...

Page 67: ...t A bis mode Direct interface to industry standard CODECs Analog Interface Chips AICs and other serially connected A D and D A devices Works with SPI compatible devices Two 16 x 16 level FIFO for Transmit channel Two 16 x 16 level FIFO for Receive channel The following application interfaces can be supported on the McBSP T1 E1 framers MVIP switching compatible and ST BUS compliant devices includin...

Page 68: ...1 RX FIFO _0 RX FIFO _15 RX FIFO _1 RX FIFO _0 McBSP Transmit Interrupt Select Logic TX FIFO Interrupt TX FIFO Registers MXINT To CPU TX Interrupt Logic 16 16 16 TX FIFO _15 TX FIFO _1 TX FIFO _0 TX FIFO _15 TX FIFO _1 TX FIFO _0 Peripheral Write Bus SM320F2812 HT SGUS062B JUNE 2009 REVISED JUNE 2011 www ti com Figure 4 9 shows the block diagram of the McBSP module with FIFO interfaced to the F281...

Page 69: ...L REGISTERS MCR2 0C R W 0x0000 McBSP Multichannel Register 2 MCR1 0D R W 0x0000 McBSP Multichannel Register 1 RCERA 0E R W 0x0000 McBSP Receive Channel Enable Register Partition A RCERB 0F R W 0x0000 McBSP Receive Channel Enable Register Partition B XCERA 10 R W 0x0000 McBSP Transmit Channel Enable Register Partition A XCERB 11 R W 0x0000 McBSP Transmit Channel Enable Register Partition B PCR 12 R...

Page 70: ... 2 Top of transmit FIFO DXR2 02 W 0x0000 Write First FIFO pointers does not advance McBSP Data Transmit Register 1 Top of transmit FIFO DXR1 03 W 0x0000 Write Second for FIFO pointers to advance FIFO Control Registers MFFTX 20 R W 0xA000 McBSP Transmit FIFO Register MFFRX 21 R W 0x201F McBSP Receive FIFO Register MFFCT 22 R W 0x0000 McBSP FIFO Control Register MFFINT 23 R W 0x0000 McBSP FIFO Inter...

Page 71: ...ammable to 64K different rates Baud rate when BRR 0 when BRR 0 Data word format One start bit Data word length programmable from one to eight bits Optional even odd no parity bit One or two stop bits Four error detection flags parity overrun framing and break detection Two wake up multiprocessor modes idle line and address bit Half or full duplex operation Double buffered receive and transmit func...

Page 72: ...er SCIFFRXA 0x00 705B 1 SCI A FIFO Receive Register SCIFFCTA 0x00 705C 1 SCI A FIFO Control Register SCIPRIA 0x00 705F 1 SCI A Priority Control Register 1 Shaded registers are new registers for the FIFO mode Table 4 9 SCI B Registers 1 2 NAME ADDRESS SIZE 16 DESCRIPTION SCICCRB 0x00 7750 1 SCI B Communications Control Register SCICTL1B 0x00 7751 1 SCI B Control Register 1 SCIHBAUDB 0x00 7752 1 SCI...

Page 73: ... SCIRXST 5 1 TX FIFO _1 TX FIFO _15 8 TX FIFO registers TX FIFO TX Interrupt Logic TXINT SCIFFTX 14 RX FIFO _15 SCIRXBUF 7 0 Receive Data Buffer register SCIRXBUF 7 0 RX FIFO_1 RX FIFO _0 8 RX FIFO registers SCICTL1 0 RX Interrupt Logic RXINT RX FIFO SCIFFRX 15 RXFFOVF RX Error SCIRXST 7 PE FE OE RX Error SCIRXST 4 2 To CPU To CPU AutoBaud Detect logic SCICTL1 1 SCIFFENA Interrupts Interrupts SM32...

Page 74: ...imum Data word length one to sixteen data bits Four clocking schemes controlled by clock polarity and clock phase bits include Falling edge without phase delay SPICLK active high SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal Falling edge with phase delay SPICLK active high SPI transmits data one half cycle ahead of the falling...

Page 75: ...r SPIRXEMU 0x00 7046 1 SPI Receive Emulation Buffer Register SPIRXBUF 0x00 7047 1 SPI Serial Input Buffer Register SPITXBUF 0x00 7048 1 SPI Serial Output Buffer Register SPIDAT 0x00 7049 1 SPI Serial Data Register SPIFFTX 0x00 704A 1 SPI FIFO Transmit Register SPIFFRX 0x00 704B 1 SPI FIFO Receive Register SPIFFCT 0x00 704C 1 SPI FIFO Control Register SPIPRI 0x00 704F 1 SPI Priority Control Registe...

Page 76: ... RX FIFO _15 TX FIFO registers TX FIFO _0 TX FIFO _1 TX FIFO _15 RX FIFO registers 16 16 16 TX Interrupt Logic RX Interrupt Logic SPIINT SPIRXINT SPITXINT SPIFFOVF FLAG SPIFFRX 15 16 TX FIFO Interrupt RX FIFO Interrupt SPIRXBUF SPITXBUF SPIFFTX 14 SPIFFENA SPISTE SPISTE is driven low by the master for a slave device SM320F2812 HT SGUS062B JUNE 2009 REVISED JUNE 2011 www ti com Figure 4 11 is a blo...

Page 77: ...ualification Control Register reserved 0x00 70CF 1 GPEMUX 0x00 70D0 1 GPIO E Mux Control Register GPEDIR 0x00 70D1 1 GPIO E Direction Control Register GPEQUAL 0x00 70D2 1 GPIO E Input Qualification Control Register reserved 0x00 70D3 1 GPFMUX 0x00 70D4 1 GPIO F Mux Control Register GPFDIR 0x00 70D5 1 GPIO F Direction Control Register reserved 0x00 70D6 1 reserved 0x00 70D7 1 GPGMUX 0x00 70D8 1 GPI...

Page 78: ...DTOGGLE 0x00 70EF 1 GPIO D Toggle Register GPEDAT 0x00 70F0 1 GPIO E Data Register GPESET 0x00 70F1 1 GPIO E Set Register GPECLEAR 0x00 70F2 1 GPIO E Clear Register GPETOGGLE 0x00 70F3 1 GPIO E Toggle Register GPFDAT 0x00 70F4 1 GPIO F Data Register GPFSET 0x00 70F5 1 GPIO F Set Register GPFCLEAR 0x00 70F6 1 GPIO F Clear Register GPFTOGGLE 0x00 70F7 1 GPIO F Toggle Register GPGDAT 0x00 70F8 1 GPIO...

Page 79: ... same all 0 s or all 1 s This feature removes unwanted spikes from the input signal Figure 4 12 GPIO Peripheral Pin Multiplexing NOTE The input function of the GPIO pin and the input path to the peripheral are always enabled It is the output function of the GPIO pin that is multiplexed with the output path of the primary peripheral function Since the output buffer of a pin connects back to the inp...

Page 80: ... TMDX through fully qualified production devices tools TMS TMDS TMX Experimental device that is not necessarily representative of the final device s electrical specifications TMP Final silicon die that conforms to the device s electrical specifications but has not completed quality and reliability verification TMS SM Fully qualified production device SMJ Fully qualified production device Support t...

Page 81: ...log multiplexers MUXs sample and hold S H circuits the conversion core voltage regulators and other analog supporting circuits Digital circuits referred to as the wrapper in this document include programmable conversion sequencer result registers interface to analog circuits interface to device peripheral bus and interface to other on chip modules TMS320x281x Boot ROM Reference Guide SPRU095 descr...

Page 82: ... and switching signals such as a motor control system In addition software techniques such as Random PWM method can be used by special features of the Texas Instruments TI TMS320x24xx DSP controllers to significantly reduce noise effects caused by EMI radiation This application report reviews designs of 3 3 V DSP versus 5 V DSP for low HP motor control applications The application report first des...

Page 83: ...74 use the commentsatbooks sc ti com email address which is a repository for feedback For questions and support contact the Product Information Center listed at http www ti com sc docs pic home htm Copyright 2009 2011 Texas Instruments Incorporated Development Support 83 Submit Documentation Feedback Product Folder Link s SM320F2812 HT ...

Page 84: ...um rated conditions for extended periods may affect device reliability All voltage values are with respect to VSS xxx VALUE UNIT Supply voltage range VDDIO VDDA1 VDDA2 VDDAIO and 0 3 to 4 6 V AVDDREFBG Supply voltage range VDD VDD1 0 5 to 2 5 V VDD3VFL range 0 3 to 4 6 V Input voltage range VIN 0 3 to 4 6 V Output voltage range VO 0 3 to 4 6 V Input clamp current IIK VIN 0 or VIN VDDIO 1 20 mA Out...

Page 85: ...GPIOA0 GPIOA15 and GPIOD0 are 4 mA drive 6 3 Electrical Characteristics Over recommended operating conditions unless otherwise noted 1 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IOH IOHMAX 2 4 VOH High level output voltage V VDDIO IOH 50 μA 0 2 VOL Low level output voltage IOL IOLMAX 0 4 V All I Os 2 including XRS 80 140 190 VDDIO 3 3 V Input except EVB With pullup VIN 0 V IIL current μA GPIOB EVB...

Page 86: ...T Life Expectancy Curve Notes 1 See data sheet for absolute maximum and minimum recommended operating conditions 2 Silicon operating life design goal is 10 years at 105 C junction temperature does not include package interconnect life 86 Electrical Specifications Copyright 2009 2011 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT ...

Page 87: ...ed IDLE 125 mA 150 mA 5 mA 10 mA 2 μA 4 μA 1 μA 35 μA 200 mA 10 mA 56 μA 100 μA 320 μA 450 μA off All peripheral clocks are on except ADC Flash is powered down Peripheral clocks STANDBY are turned off 5 mA 10 mA 5 μA 20 μA 2 μA 4 μA 1 μA 35 μA 27 mA 40 mA 160 μA 200 μA 56 μA 100 μA 320 μA 450 μA Pins without an internal PU PD are tied high low Flash is powered down Peripheral clocks are turned off...

Page 88: ...cess voltage and temperature conditions B IDD represents the total current drawn from the 1 8 V rail VDD It includes a trivial amount of current 1 mA drawn by VDD1 C IDDA represents the current drawn by VDDA1 and VDDA2 rails D Total 3 3 V current is the sum of IDDIO IDD3VFL and IDDA It includes a trivial amount of current 1 mA drawn by VDDAIO Figure 6 2 Typical Current Consumption Over Frequency F...

Page 89: ... two options for the power sequencing circuit Option 1 In this approach an external power sequencing circuit enables VDDIO first then VDD and VDD1 1 8 V or 1 9 V After 1 8 V or 1 9 V ramps the 3 3 V for Flash VDD3VFL and ADC VDDA1 VDDA2 AVDDREFBG modules are ramped up While option 1 is still valid TI has simplified the requirement Option 2 is the recommended approach Option 2 Enable power to all 3...

Page 90: ...xxx NOTE The GPIO pins are undefined until VDD 1 V and VDDIO 2 5 V Figure 6 4 F2812 Typical Power Up and Power Down Sequence Option 2 90 Electrical Specifications Copyright 2009 2011 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT ...

Page 91: ...nger low is 20 of the total voltage range and higher and the level at which the output is said to be high is 80 of the total voltage range and higher Figure 6 6 shows the input levels Figure 6 6 Input Levels Input transition times are specified as follows For a high to low transition on an input signal the level at which the input is said to be no longer high is 90 of the total voltage range and l...

Page 92: ...the pin names and other related terminology have been abbreviated as follows Lowercase subscripts and their meanings Letters and symbols and their meanings a access time H High c cycle time period L Low d delay time V Valid f fall time X Unknown changing or don t care level h hold time Z High impedance r rise time su setup time t transition time v valid time w pulse duration width 6 10 General Not...

Page 93: ...k Frequency 25 MHz tc SPC Cycle time 50 ns SPI clock Frequency 20 MHz tc CKG Cycle time 50 ns McBSP Frequency 20 MHz tc XTIM Cycle time 6 67 ns XTIMCLK Frequency 150 MHz 1 This is the default reset value if SYSCLKOUT 150 MHz 2 The maximum value for ADCCLK frequency is 25 MHz For SYSCLKOUT values of 25 MHz or lower ADCCLK has to be SYSCLKOUT 2 or lower ADCCLK SYSCLKOUT is not a valid mode for any v...

Page 94: ...ut to the PLL Disabled XCLKIN CPU CLKIN is directly derived from the clock signal present at the X1 XCLKIN pin Default PLL configuration upon power up if PLL is not disabled The PLL itself is bypassed PLL Bypassed However the 2 module in the PLL block divides the clock input at the X1 XCLKIN pin by two before XCLKIN 2 feeding it to the CPU Achieved by writing a non zero value n into PLLCR register...

Page 95: ...ata valid after XRS high 32tc CI cycles tOSCST 3 Oscillator start up time 1 10 ms tsu XPLLDIS Setup time for XPLLDIS pin 16tc CI cycles th XPLLDIS Hold time for XPLLDIS pin 16tc CI cycles th XMP MC Hold time for XMP MC pin 16tc CI cycles th boot mode Hold time for boot mode pins 2520tc CI 4 cycles 1 If external oscillator clock source isused reset time has to be low at least for 1 ms after VDD rea...

Page 96: ...ts in the XINTCNF2 register come up with a reset state of 1 SYSCLKOUT is further divided by 4 before it appears at XCLKOUT This explains why XCLKOUT XCLKIN 8 during this phase D After reset the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles SYSCLKOUT XCLKIN 2 and then samples BOOT Mode pins Based on the status of the Boot Mode pin the boot code branches to destination memory or boot...

Page 97: ...LKIN 2 if the PLL is enabled Since both the XTIMCLK and CLKMODE bits in the XINTCNF2 register come up with a reset state of 1 SYSCLKOUT is further divided by 4 before it appears at XCLKOUT This explains why XCLKOUT XCLKIN 8 during this phase B The state of the GPIO pins is undefined i e they could be input or output until the 1 8 V or 1 9 V supply reaches at least 1 V and 3 3 V supply reaches 2 5 ...

Page 98: ...Long XCLKIN x 4 Changed CPU Frequency SM320F2812 HT SGUS062B JUNE 2009 REVISED JUNE 2011 www ti com A After reset the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles SYSCLKOUT XCLKIN 2 and then samples BOOT Mode pins Based on the status of the Boot Mode pin the boot code branches to destination memory or boot code function in ROM The BOOT Mode pins should be held high low for at leas...

Page 99: ...s Flash module in active state td WAKE IDLE Wake up from Flash Without input qualifier 1050 tc SCO Cycles Flash module in sleep state Wake up from Flash With input qualifier 1050 tc SCO IQT 2 Cycles Flash module in sleep state Wake up from SARAM Without input qualifier 8 tc SCO Cycles Wake up from SARAM With input qualifier 8 tc SCO IQT 2 Cycles 1 Not production tested 2 Input Qualification Time I...

Page 100: ...ash Flash module in active With input qualifier 12 tc CI tw WAKE INT Cycles state td WAKE STBY Wake up from Flash Without input Flash module in sleep 1125 tc SCO Cycles qualifier state Wake up from Flash Flash module in sleep With input qualifier 1125 tc SCO tw WAKE INT Cycles state Without input Wake up from SARAM 12 x tc CI Cycles qualifier Wake up from SARAM With input qualifier 12 tc CI tw WAK...

Page 101: ...y enables the CPU pipe and any other pending operations to flush properly C The device is now in STANDBY mode D The external wake up signal is driven active negative edge triggered shown as an example E After a latency period the STANDBY mode is exited F Normal operation resumes The device responds to the interrupt if enabled SM320F2812 HT www ti com SGUS062B JUNE 2009 REVISED JUNE 2011 Figure 6 1...

Page 102: ...NMI wakeup signal 2 tc CI Cycles tw WAKE XRS Pulse duration XRS wakeup signal 8 tc CI Cycles tp PLL lock up time 131 072 tc CI Cycles Delay time PLL lock to program execution resume Wake up from flash td wake 1125 tc SCO Cycles Flash module in sleep state Wake up from SARAM 35 tc SCO Cycles 1 Not production tested 102 Electrical Specifications Copyright 2009 2011 Texas Instruments Incorporated Sub...

Page 103: ...mes absolute minimum power D When XNMI is friven active negative edge triggered shown as an example the oscillator is turned on but the PLL is not activiated E When XNMI is deactiveted it initiates the PLL lock sequence which takes 131 072 X1 XCLKIN cycles F When CLKIN to the core is enabled the device responds to the interrupt if enabled after a latency The HALT mode is now exited G Normal operat...

Page 104: ...as a percentage of TCLKINx cycle time 40 60 tw TCLKINH Pulse duration TCLKINx high as a percentage of TCLKINx cycle time 40 60 tc TCLKIN Cycle time TCLKINx 4 tc HCO ns 1 The QUALPRD bit field value can range from 0 no qualification through 0xFF 510 SYSCLKOUT cycles The qualification sampling period is 2n SYSCLKOUT cycles where n is the value stored in the QUALPRD bit field As an example when QUALP...

Page 105: ...cle tw EVBSOCL Pulse duration EVBSOC low 32 tc HCO ns 1 XCLKOUT SYSCLKOUT 2 Not production tested Figure 6 19 EVBSOC Timing 6 16 2 Interrupt Timing Table 6 17 Interrupt Switching Characteristics PARAMETER MIN MAX UNIT Without input 12 qualifier Delay time PDPINTx low to PWM td PDP PWM HZ ns high impedance state 1 tc SCO IQT With input qualifier 12 1 Without input 3 tc SCO Delay time CxTRIP TxCTRIP...

Page 106: ...on Time IQT 5 QUALPRD 2 tc SCO A XCLKOUT SYSCLKOUT B TxCTRIP T1CTRIP T2CTRIP T3CTRIP T4CTRIP CxTRIP C1TRIP C2TRIP C3TRIP C4TRIP C5TRIP or C6TRIP PDPINTx PDPINTA or PDPINTB C PWM refers to all the PWM pins in the device i e PWMn and TnPWM pins or PWM pin pair relevant to each CxTRIP pin The state of the PWM pins after PDPINTx is taken high depends on the state of the FCOMPOE bit Figure 6 20 Externa...

Page 107: ... cycles or greater In other words the inputs should be stable for 5 x QUALPRD x 2 SYSCLKOUT cycles This would ensure six sampling windows for detection to occur Since external signals are driven asynchronously an 11 SYSCLKOUT wide pulse ensures reliable recognition See Note A SM320F2812 HT www ti com SGUS062B JUNE 2009 REVISED JUNE 2011 Figure 6 21 General Purpose Output Timing 6 18 General Purpos...

Page 108: ...M 0 5tc SPC M 0 5tc LCO 10 0 5tc SPC M 0 5tc LCO clock polarity 1 Delay time SPICLK high to SPISIMO td SPCH SIMO M 10 10 10 10 valid clock polarity 0 4 4 ns Delay time SPICLK low to SPISIMO td SPCL SIMO M 10 10 10 10 valid clock polarity 1 Valid time SPISIMO data valid after tv SPCL SIMO M 0 5tc SPC M 10 0 5tc SPC M 0 5tc LCO 10 SPICLK low clock polarity 0 5 4 ns Valid time SPISIMO data valid afte...

Page 109: ...SPI clock speed is not greater than the I O buffer speed limit 20 MHz A In the master mode SPISTE goes active 0 5tc SPC before valid SPI clock edge On the trailing end of the word the SPISTE will go inactive 0 5tc SPC after the receiving edge SPICLK of the last data bit Figure 6 24 SPI Master Mode External Timing Clock Phase 0 Copyright 2009 2011 Texas Instruments Incorporated Electrical Specifica...

Page 110: ...H M before SPICLK high clock 0 5tc SPC M 10 0 5tc SPC M 10 polarity 0 6 4 ns Setup time SPISIMO data valid tsu SIMO SPCL M before SPICLK low clock 0 5tc SPC M 10 0 5tc SPC M 10 polarity 1 Valid time SPISIMO data valid tv SPCH SIMO M after SPICLK high clock polarity 0 5tc SPC M 10 0 5tc SPC M 10 0 7 4 ns Valid time SPISIMO data valid tv SPCL SIMO M after SPICLK low clock polarity 0 5tc SPC M 10 0 5...

Page 111: ...ED JUNE 2011 A In the master mode SPISTE goes active 0 5tc SPC before valid SPI clock edge On the trailing end of the word the SPISTE will go inactive 0 5tc SPC after the receiving edge SPICLK of the last data bit Figure 6 25 SPI Master External Timing Clock Phase 1 Copyright 2009 2011 Texas Instruments Incorporated Electrical Specifications 111 Submit Documentation Feedback Product Folder Link s ...

Page 112: ...C S 10 Valid time SPISOMI data valid after SPICLK low tv SPCL SOMI S 0 75tc SPC S clock polarity 0 16 4 ns Valid time SPISOMI data valid after SPICLK high tv SPCH SOMI S 0 75tc SPC S clock polarity 1 tsu SIMO SPCL S Setup time SPISIMO before SPICLK low clock polarity 0 0 19 4 ns tsu SIMO SPCH S Setup time SPISIMO before SPICLK high clock polarity 1 0 Valid time SPISIMO data valid after SPICLK low ...

Page 113: ...d time SPIS OMI data valid after SPICLK high tv SPCH SOMI S 0 75tc SPC S clock polarity 0 18 4 ns Valid time SPISOMI data valid after SPICLK low tv SPCL SOMI S 0 75tc SPC S clock polarity 1 Setup time SPISIMO before SPICLK high tsu SIMO SPCH S 0 clock polarity 0 21 5 ns Setup time SPISIMO before SPICLK low tsu SIMO SPCL S 0 clock polarity 1 Valid time SPISIMO data valid after SPICLK high tv SPCH S...

Page 114: ...n of Pulse 1 2 3 DURATION ns DESCRIPTION X2TIMING 0 X2TIMING 1 LR Lead period read access XRDLEAD tc XTIM XRDLEAD 2 tc XTIM AR Active period read access XRDACTIVE WS 1 tc XTIM XRDACTIVE 2 WS 1 tc XTIM TR Trail period read access XRDTRAIL tc XTIM XRDTRAIL 2 tc XTIM LW Lead period write access XWRLEAD tc XTIM XWRLEAD 2 tc XTIM AW Active period write access XWRACTIVE WS 1 x tc XTIM XWRACTIVE 2 WS 1 t...

Page 115: ...c XTIM AW 2 tc XTIM NOTE Restriction does not include external hardware wait states These requirements result in the following XTIMING register configuration restrictions Table 6 28 XTIMING Register Configuration Restrictions 1 2 XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING 1 1 0 1 1 0 0 1 1 Not production tested 2 No hardware to detect illegal XTIMING configurations Examples of ...

Page 116: ... 0 2 1 0 0 1 1 Not production tested 2 No hardware to detect illegal XTIMING configurations Examples of valid and invalid timing when using Asynchronous XREADY Table 6 32 Asynchronous XREADY 1 2 XRDLEAD XRDACTIVE XRDTRAIL XWRLEAD XWRACTIVE XWRTRAIL X2TIMING Invalid 0 0 0 0 0 0 0 1 Invalid 1 0 0 1 0 0 0 1 Invalid 1 1 0 1 1 0 0 Valid 1 1 0 1 1 0 1 Valid 1 2 0 1 2 0 0 1 Valid 2 1 0 2 1 0 0 1 1 Not pr...

Page 117: ...6 33 XINTF Clock Configurations continued MODE SYSCLKOUT XTIMCLK XCLKOUT 3 1 2 SYSCLKOUT 1 2 SYSCLKOUT Example 150 MHz 75 MHz 75 MHz 4 1 2 SYSCLKOUT 1 4 SYSCLKOUT Example 150 MHz 75 MHz 37 5 MHz The relationship between SYSCLKOUT and XTIMCLK is shown in Figure 6 28 Figure 6 28 Relationship Between XTIMCLK and SYSCLKOUT Copyright 2009 2011 Texas Instruments Incorporated Electrical Specifications 11...

Page 118: ...LKOUT Examples include the following Strobes that change at the beginning of an access always align to the rising edge of XCLKOUT This is because all XINTF accesses begin with respect to the rising edge of XCLKOUT Examples XZCSL Zone chip select active low XRNWL XR W active low Strobes that change at the beginning of the active period aligns to the rising edge of XCLKOUT if the total number of lea...

Page 119: ...e chip select inactive high 2 3 ns td XCOH XA Delay time XCLKOUT high to address valid 2 ns td XCOHL XRDL Delay time XCLKOUT high low to XRD active low 1 ns td XCOHL XRDH Delay time XCLKOUT high low to XRD inactive high 2 1 ns th XA XZCSH Hold time address valid after zone chip select inactive high 2 ns th XA XRD Hold time address valid after XRD inactive high 2 ns 1 Not production tested 2 During...

Page 120: ...e Switching Characteristics 1 PARAMETER MIN MAX UNIT td XCOH XZCSL Delay time XCLKOUT high to zone chip select active low 1 ns td XCOHL XZCSH Delay time XCLKOUT high or low to zone chip select inactive high 2 3 ns td XCOH XA Delay time XCLKOUT high to address valid 2 ns td XCOHL XWEL Delay time XCLKOUT high low to XWE low 2 ns td XCOHL XWEH Delay time XCLKOUT high low to XWE high 2 ns td XCOH XRNW...

Page 121: ... example XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE N A 1 N A 1 N A 1 0 0 1 0 0 N A 1 1 N A Don t care for this example Copyright 2009 2011 Texas Instruments Incorporated Electrical Specifications 121 Submit Documentation Feedback Product Folder Link s SM320F2812 HT ...

Page 122: ...YsynchH Earliest time XREADY Synch can go high before the sampling XCLKOUT edge 3 ns tsu XRDYsynchH XCOHL Setup time XREADY Synch high before XCLKOUT high low 15 ns th XRDYsynchH XZCSH Hold time XREADY Synch held high after zone chip select high 0 ns 1 Not production tested 2 The first XREADY Synch sample occurs with respect to E in Figure 6 31 E XRDLEAD XRDACTIVE tc XTIM When first sampled if XRE...

Page 123: ...AD XRDACTIVE tc XTIM where n is the sample number n 1 2 3 and so forth th XRDYsynchL tsu XRDYsynchL XCOHL tsu XD XRD ta XRD ta A th XD XRD th XRDYsynchH XZCSH Don t care Signal can be high or low during this time Legend tsu XRDHsynchH XCOHL See Note D See Note E te XRDYsynchH See Note D See Notes A and B See Note C SM320F2812 HT www ti com SGUS062B JUNE 2009 REVISED JUNE 2011 Table 6 40 Asynchrono...

Page 124: ...EAD XRDACTIVE 3 n tc XTIM tsu XRDYasynchL XCOHL where n is the sample number n 1 2 3 and so forth E Reference for the first sample is with respect to this point E XRDLEAD XRDACTIVE 2 tc XTIM tsu XRDYasynchL XCOHL ta XRD ta A th XRDYasynchL th XD XRD th XRDYasynchH XZCSH Don t care Signal can be high or low during this time Legend See Note C tsu XRDYasynchH XCOHL See Note D See Note E te XRDYasynch...

Page 125: ... XCOHL Setup time XREADY Synch high before XCLKOUT high low 15 ns th XRDYsynchH XZCSH Hold time XREADY Synch held high after zone chip select high 0 ns 1 Not production tested 2 The first XREADY Synch sample occurs with respect to E in Figure 6 33 E XWRLEAD XWRACTIVE tc XTIM When first sampled if XREADY Synch is found to be high then the access completes If XREADY Synch is found to be low it is sa...

Page 126: ...chL XCOHL where n is the sample number n 1 2 3 and so forth E Reference for the first sample is with respect to this point E XWRLEAD XWRACTIVE tc XTIM td XCOH XRNWL td XCOHL XRNWH ten XD XWEL th XD XWEH tsu XRDHsynchH XCOHL tsu XRDYsynchL XCOHL DOUT td XWEL XD tdis XD XRNW th XRDYsynchL th XRDYsynchH XZCSH Don t care Signal can be high or low during this time Legend See Note E See Note D See Notes...

Page 127: ... is the sample number n 1 2 3 and so forth E Reference for the first sample is with respect to this point E XWRLEAD XWRACTIVE 2 tc XTIM td XCOH XRNWL td XCOHL XRNWH ten XD XWEL th XD XWEH th XRDYasynchL DOUT tdis XD XRNW th XRDYasynchH XZCSH See Note E See Note D Don t care Signal can be high or low during this time Legend tsu XRDYasynchL XCOHL tsu XRDYasynchH XCOHL td XWEL XD td XCOHL XWEL te XRD...

Page 128: ...HOLD mode is enabled and XHOLDA is active low external bus grant active the CPU can still execute code from internal memory If an access is made to the external interface the CPU is stalled until the XHOLD signal is removed An external DMA request when granted places the following signals in a high impedance mode XA 18 0 XZCS0AND1 XD 15 0 XZCS2 XWE XRD XZCS6AND7 XR W All other signals not listed i...

Page 129: ...lay time XHOLD low to XHOLDA low 5tc XTIM ns td HH HAH Delay time XHOLD high to XHOLDA high 3tc XTIM ns td HH BV Delay time XHOLD high to Bus valid 4tc XTIM ns 1 When a low signal is detected on XHOLD all pending XINTF accesses are completed before the bus is placed in a high impedance state 2 The state of XHOLD is latched on the rising edge of XTIMCLK 3 Not production tested A All pending XINTF a...

Page 130: ... are completed before the bus is placed in a high impedance state 2 The state of XHOLD is latched on the rising edge of XTIMCLK 3 After the XHOLD is detected low or high all bus transitions and XHOLDA transitions occur with respect to the rising edge of XCLKOUT Thus for this mode where XCLKOUT 1 2 XTIMCLK the transitions can occur up to 1 XTIMCLK cycle earlier than the maximum value specified 4 No...

Page 131: ...ed over operating conditions Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only Exposure to absolute maximum rated conditions for extended periods may affect device reliability 2 The analog inputs have an internal clamping circuit that clamps the voltage to a diode drop above VDDA or below VSS The continuous clamp curr...

Page 132: ... MHz ADC clock SYSCLKOUT 2 4 The INL degrades for frequencies beyond 18 75 MHz 25 MHz Applications that require these sampling rates should use a 20 kΩ resistor as bias resistor on the ADCRESEXT pin This improves overall linearity and typical current drawn by the ADC is a few mA more than 24 9 kW bias 5 1 LSB has the weighted value of 3 0 4096 0 732 mV 6 A single internal band gap reference 5 accu...

Page 133: ...Current Consumption for Different ADC Configurations at 25 MHz ADCCLK Table 6 48 Current Consumption 1 IDDA TYP 2 IDDAIO TYP IDD1 TYP ADC OPERATING MODE CONDITIONS 3 Mode A Operational Mode 40 mA 1 μA 0 5 mA BG and REF enabled PWD disabled Mode B ADC clock enabled 7 mA 0 5 μA BG and REF enabled PWD enabled Mode C ADC clock enabled 1 μA 0 5 μA BG and REF disabled PWD enabled Mode D ADC clock disabl...

Page 134: ...T Delay time for band gap reference to be stable Bits 6 and 5 of the ADCTRL3 register td BGR 7 8 10 ms PWDNBG and PWDNREF are to be set to 1 before the ADCPWDN bit is enabled 20 50 μs Delay time for power down control to be stable Bit 7 of the ADCTRL3 register ADCPWDN td PWD is to be set to 1 before any ADC conversions are initiated 1 ms 1 These delays are necessary and recommended to make the ADC...

Page 135: ...rsion modes Sequential sampling mode SMODE 0 Simultaneous sampling mode SMODE 1 6 29 6 Sequential Sampling Mode Single Channel SMODE 0 In sequential sampling mode the ADC can continuously convert input signals on any of the channels Ax to Bx The ADC can start conversions on event triggers from the Event Managers EVA EVB software trigger or from an external ADCSOC signal If the SMODE bit is 0 the A...

Page 136: ...e 0 15 tSH Sample Hold width Acquisition width 40 ns with Acqps 0 tc ADCCLK ADCTRL1 8 11 Delay time for first result to appear td schx_n 4tc ADCCLK 160 ns in the Result register Delay time for successive results to 2 Acqps td schx_n 1 80 ns appear in the Result register tc ADCCLK 1 Not production tested 136 Electrical Specifications Copyright 2009 2011 Texas Instruments Incorporated Submit Documen...

Page 137: ...he Sample Hold pulse The Sample Hold pulse width can be programmed to be 1 ADC clock wide minimum or 16 ADC clocks wide maximum NOTE In Simultaneous mode the ADCIN channel pair select has to be A0 B0 A1 B1 A7 B7 and not in other combinations such as A1 B3 etc Figure 6 40 Simultaneous Sampling Mode Timing Table 6 51 Simultaneous Sampling Mode Timing 1 AT 25 MHz ADC SAMPLE n SAMPLE n 1 CLOCK REMARKS...

Page 138: ...LSB below the nominal full scale Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions 6 29 8 5 Signal to Noise Ratio Distortion SINAD SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency including harmonics ...

Page 139: ... time DR valid before CLKR low ns CLKR ext 2 CLKR int 0 M18 th CKRL DRV Hold time DR valid after CLKR low ns CLKR ext 6 CLKX int 18 M19 tsu FXH CKXL Setup time external FSX high before CLKX low ns CLKX ext 2 CLKX int 0 M20 th CKXL FXH Hold time external FSX high after CLKX low ns CLKX ext 6 1 Polarity bits CLKRP CLKXP FSRP FSXP 0 If the polarity of any of the signals is inverted then the timing re...

Page 140: ...ed when in Data DXENA 1 Delay 1 or 2 XDATDLY 01b or 10b modes CLKX ext P 14 CLKX int 0 Enable time CLKX high to DX driven DXENA 0 CLKX ext 6 M8 ten CKXH DX ns CLKX int P Only applies to first bit transmitted when in Data DXENA 1 Delay 1 or 2 XDATDLY 01b or 10b modes CLKX ext P 6 FSX int 8 Delay time FSX high to DX valid DXENA 0 FSX ext 14 M9 td FXH DXV ns FSX int P 8 Only applies to first bit tran...

Page 141: ...Y 01b DX XDATDLY 00b DX n 2 Bit n 1 Bit 0 n 4 Bit n 1 n 3 n 2 Bit 0 n 3 n 2 Bit n 1 Bit 0 M20 M14 M13 M3 M12 M1 M11 M2 M12 FSX ext FSX int CLKX M5 M5 M19 SM320F2812 HT www ti com SGUS062B JUNE 2009 REVISED JUNE 2011 Figure 6 41 McBSP Receive Timing Figure 6 42 McBSP Transmit Timing Copyright 2009 2011 Texas Instruments Incorporated Electrical Specifications 141 Submit Documentation Feedback Produc...

Page 142: ...witching Characteristics CLKSTP 10b CLKXP 0 1 2 MASTER SLAVE NO PARAMETER UNIT MIN MAX MIN MAX M24 th CKXL0FXL Hold time FSX low after CLKX low 2P ns M25 td FXL0CKXH Delay time FSX low to CLKX high P ns Disable time DX high impedance following last data bit from M28 tdis FXH0DXHZ 6 6P 6 ns FSX high M29 td FXL0DXV Delay time FSX low to DX valid 6 4P 6 ns 1 Not production tested 2 2P 1 CLKG For all ...

Page 143: ...cs CLKSTP 11b CLKXP 0 1 2 MASTER SLAVE NO PARAMETER UNIT MIN MAX MIN MAX M34 th CKXL FXL Hold time FSX low after CLKX low P ns M35 td FXL CKXH Delay time FSX low to CLKX high 2P ns Disable time DX high impedance following last data bit M37 tdis CKXL DXHZ P 6 7P 6 ns from CLKX low M38 td FXL DXV Delay time FSX low to DX valid 6 4P 6 ns 1 Not production tested 2 2P 1 CLKG For all SPI slave modes CLK...

Page 144: ...ics CLKSTP 10b CLKXP 1 1 2 MASTER SLAVE NO PARAMETER UNIT MIN MAX MIN MAX M43 th CKXH FXL Hold time FSX low after CLKX high 2P ns M44 td FXL CKXL Delay time FSX low to CLKX low P ns Disable time DX high impedance following last data bit from FSX M47 tdis FXH DXHZ 6 6P 6 ns high M48 td FXL DXV Delay time FSX low to DX valid 6 4P 6 ns 1 Not production tested 2 2P 1 CLKG For all SPI slave modes CLKX ...

Page 145: ...ASTER 3 SLAVE NO PARAMETER UNIT MIN MAX MIN MAX M53 th CKXH FXL Hold time FSX low after CLKX high P ns M54 td FXL CKXL Delay time FSX low to CLKX low 2P ns Disable time DX high impedance following last data bit from CLKX M56 tdis CKXH DXHZ P 6 7P 6 ns high M57 td FXL DXV Delay time FSX low to DX valid 6 4P 6 ns 1 Not production tested 2 2P 1 CLKG For all SPI slave modes CLKX has to be minimum eigh...

Page 146: ...lder silicon revisions the write erase cycle numbers of 100 MIN and 1000 TYP are applicable Table 6 63 Flash Parameters at 150 MHz SYSCLKOUT 1 2 PARAMETER MIN TYP MAX UNIT 16 Bit Word 35 μs Program 8K Sector 170 ms Time 16K Sector 320 ms 8K Sector 10 s Erase Time 16K Sector 11 s Erase 75 mA IDD3VFLP VDD3VFL current consumption during the Erase Program cycle Program 35 mA IDDP VDD current consumpti...

Page 147: ... 3 150 6 67 5 5 120 8 33 4 4 100 10 3 3 75 13 33 2 2 50 20 1 1 30 33 33 1 1 25 40 0 1 15 66 67 0 1 4 250 0 1 1 Not production tested 2 Formulas to compute page wait state and random wait state 3 Random wait state must be greater than or equal to 1 Copyright 2009 2011 Texas Instruments Incorporated Electrical Specifications 147 Submit Documentation Feedback Product Folder Link s SM320F2812 HT ...

Page 148: ...l Data The following mechanical package diagram s reflect the most current released mechanical data available for the designated device s 148 Mechanical Data Copyright 2009 2011 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s SM320F2812 HT ...

Page 149: ...er from page numbers in the current version Changes from A Revision April 2010 to B Revision Page Changed Table 3 31 1 Recommended Operating Conditions to Table 6 62 Flash Endurance Timing 146 Copyright 2009 2011 Texas Instruments Incorporated Mechanical Data 149 Submit Documentation Feedback Product Folder Link s SM320F2812 HT ...

Page 150: ...n specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine ...

Page 151: ...PACKAGE OPTION ADDENDUM www ti com 24 Sep 2012 Addendum Page 2 Catalog TI s standard catalog product Enhanced Product Supports Defense Aerospace and Medical Applications ...

Page 152: ......

Page 153: ...regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures monitor failures and their consequence...

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