Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 754 / 3738

Public Version
IVA2.2 Subsystem Basic Programming Model
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To ensure write-back completion of a specific buffer (contiguous address range), see Section 5.4.3.4.6 ,
Write-Back Completion, for additional programming steps and an example.
• Global write-back and block invalidate
Global write-back and block invalidate is controlled by the following registers: IVA_XMC.
L2WBINV and
IVA_XMC. L1DWBINV .
Example of global write-back and block invalidate:
/* ---------------------------------------------------- */
/* Write back and invalidate anything held in cache. */
/* ---------------------------------------------------- */
L2WBINV = 1;
/* ---------------------------------------------------- */
/* Now, spin waiting for operation to complete. */
/* ---------------------------------------------------- */
while ((L2WBINV & 1) != 0)
;
To ensure write-back completion of a specific buffer (contiguous address range), see Section 5.4.3.4.6 ,
Write-Back Completion, for additional programming steps and an example.
5.4.3.4.5 Block Cache Management
• Block invalidate
Block invalidate is controlled by the following registers: IVA_XMC.L2BAR, IVA_XMC.
L2IWC ,
IVA_XMC. L1DIBAR , IVA_XMC. L1DIWC , IVA_XMC. L1PIBAR , and IVA_XMC. L1PIWC .
Example of block invalidate:
/* ---------------------------------------------------- */
/* Write base address of array to Base Address Register. /
/* Then write length of the array, in words, to the Word*/
/* Count register. */
/* ---------------------------------------------------- */
L2IBAR = &array[0];
L2IWC = = sizeof(array) / sizeof(int);
/* . . . */
/* ---------------------------------------------------- */
/* The CPU can execute other code here. Block cache operations proceed in parallel with CPU
execution, stalling the CPU minimally. */
/* ------------------------ --------------------------- */
/* . . . */
/* ---------------------------------------------------- */
/* Now, spin waiting for operation to complete. */
/* ---------------------------------------------------- */
while (L2IWC != 0)
;
L2IWC = 0 ensures that L1D cache and L1P cache are also block invalidated before the L2 cache
invalidate process.
• Block write-back
Block write-back is controlled by the following registers: IVA_XMC.
L2WBAR , IVA_XMC. L2WWC ,
IVA_XMC. L1DWBAR , and IVA_XMC. L1DWWC .
Example of block write-back:
/* ---------------------------------------------------- */
/* Write base address of array to Base Address Register.*/
/* Then write length of array, in words, to the Word */
/* Count register. */
/* ---------------------------------------------------- */
L2WBAR = &array[0];
754 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010
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