Texas Instruments OMAP36 Series, Technical Reference Manual

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IVA2.2 Subsystem Register Manual
Bits Field Name Description Type Reset
31:1 Reserved Write 0s for future compatibility. Read returns 0. RW 0x--------
0 C L2 global write-back control RW 0
Read 0x0: Read 0: Previous L2 global write-back has
completed
Write 0x0: Write 0: No effect
Read 0x1: Read 1: Previous L2 global write-back has not
completed
Write 0x1: Write 1: Initiates an L2 global write-back(L1P Effect:
No effect. L1D Effect: All updated data written back
to L2/external, but left valid in L1D. L2 Effect: All
updated data written back externally, but left valid in
L2 cache. )
Table 5-146. Register Call Summary for Register L2WB
IVA2.2 Subsystem Basic Programming Model
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IVA2.2 Subsystem Register Manual
• XMC Register Mapping Summary : [1]
Table 5-147. L2WBINV
Address Offset 0x0000 5004
Physical address 0x0184 5004 Instance IVA2.2 GEMXMC
Description L2 global writeback invalidate
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved C
Bits Field Name Description Type Reset
31:1 Reserved Write 0s for future compatibility. Read returns 0. RW 0x--------
0 C L2 global write-back/invalidate command: RW 0
Write 0: No effect
Write 1: Initiates an L2 global write-back/invalidate(L1P Effect: All lines
invalidated in L1P. L1D Effect: All updated data written back to
L2/external. All lines invalidated within L1D. L2 Effect: All updated data
written back externally. All lines invalidated in L2).
Read 0: Previous L2 global write-back/invalidate has completed
Read 1: Previous L2 global write-back/invalidate has not completed
Table 5-148. Register Call Summary for Register L2WBINV
IVA2.2 Subsystem Basic Programming Model
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IVA2.2 Subsystem Register Manual
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843 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
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