Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 753 / 3738

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IVA2.2 Subsystem Basic Programming Model
for the completion of the write-back sequence in end memory. For a description of how the write-back
sequence occurs in the IVA2.2 subsystem, see
Section 5.4.3.4.6 , Write-Back Completion. When the
consumer receives the message, if the consumer has a cache-based architecture, updates by the
producer must be effectively seen (not a local nonupdated copy). For a description of how the invalidate
sequence occurs in the IVA2.2 subsystem, see
Section 5.4.3.4.4 , Global Cache Management.
Two types of cache coherence management are possible:
• Global cache coherence allows the DSP CPU to ensure coherence of the entire cache at once. See
Section 5.4.3.4.4 , Global Cache Management.
• Block cache coherence allows the DSP CPU to ensure coherence of a contiguous region of the virtual
address map, restricted in size to only what is needed. See
Section 5.4.3.4.5 , Block Cache
Management.
Each management type provides three sets of actions:
• Invalidate ensures that all required lines are made invalid in the cache. After that operation, any update
(before invalidate operation) in end memory by an alternate processor/DMA is seen by the DSP CPU,
forcing a cache line refill.
• Write-back ensures that all required cache lines modified by the DSP CPU (also called dirty lines) are
written back to end memory, so that any local update by the DSP CPU is made visible by an alternate
processor/DMA. This applies only to L1D cache and L2 cache, not to L1P cache.
• Write-back and invalidate ensure that all required cache lines modified by the DSP CPU (also called
dirty lines) are written back to end memory so that any local update by the DSP CPU is made visible
by an alternate processor/DMA, and they ensure that all required lines are made invalid in the cache.
After that operation, any update in end memory by an alternate processor/DMA is seen by the DSP
CPU, forcing a cache line refill. This applies only to L1D cache and L2 cache, not to L1P cache.
5.4.3.4.4 Global Cache Management
This section describes how to invalidate and write back the cache memory
• Global invalidate
Global invalidate is controlled by the following registers: IVA_XMC.
L2INV , IVA_XMC. L1DINV , and
IVA_XMC. L1PINV .
Example of global invalidate:
/* ---------------------------------------------------- */
/* Invalidate anything held in cache. */
/* ---------------------------------------------------- */
L2INV = 1;
/* ---------------------------------------------------- */
/* Now, spin waiting for operation to complete. */
/* ---------------------------------------------------- */
while ((L2INV & 1) != 0)
;
L2INV = 0 ensures that L1D cache and L1P cache are also globally invalidated before the L2 cache
invalidate process.
• Global write-back
Global write-back is controlled by the following registers: IVA_XMC.
L2WB and IVA_XMC. L1DWB .
Example of global write-back:
/* ---------------------------------------------------- */
/* Write back anything held in cache. */
/* ---------------------------------------------------- */
L2WB = 1;
/* ---------------------------------------------------- */
/* Now, spin waiting for operation to complete. */
/* ---------------------------------------------------- */
while ((L2WB & 1) != 0)
;
753 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated