Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 844 / 3738

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IVA2.2 Subsystem Register Manual
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Table 5-149. L2INV
Address Offset 0x0000 500
Physical address 0x0184 5008 Instance IVA2.2 GEMXMC
Description L2 global invalidate
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved I
Bits Field Name Description Type Reset
31:1 Reserved Write 0s for future compatibility. Read returns 0. RW 0x--------
0 I L2 global invalidate command: RW 0
Write 0: No effect
Write 1: Initiates an L2 global invalidate(L1P Effect: All lines
invalidated in L1P. L1D Effect: All lines invalidated in L1D. Updated
data is dropped. L2 Effect: All lines invalidated in L2. Updated data is
dropped).
Read 0: Previous L2 global invalidate has completed
Read 1: Previous L2 global invalidate has notcompleted
Table 5-150. Register Call Summary for Register L2INV
IVA2.2 Subsystem Basic Programming Model
• Coherence Maintenance : [0] [1]
IVA2.2 Subsystem Register Manual
• XMC Register Mapping Summary : [2]
Table 5-151. L1PINV
Address Offset 0x0000 5028
Physical address 0x0184 5028 Instance IVA2.2 GEMXMC
Description L1P Global Invalidate
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved I
Bits Field Name Description Type Reset
31:1 Reserved Write 0s for future compatibility. Read returns 0. RW 0x--------
0 I L1P global invalidate command: RW 0
Write 0: No effect
Write 1: Initiates an L1P global invalidate
Read 0: Previous L1P global invalidate has completed
Read 1: Previous L1P global invalidate has notcompleted
Table 5-152. Register Call Summary for Register L1PINV
IVA2.2 Subsystem Basic Programming Model
• Coherence Maintenance : [0]
IVA2.2 Subsystem Register Manual
• XMC Register Mapping Summary : [1]
844 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010
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