Texas Instruments OMAP36 Series, Technical Reference Manual

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IVA2.2 Subsystem Basic Programming Model
L2WWC = sizeof(array) / sizeof(int);
/* . . . */
/* ---------------------------------------------------- */
/* CPU can execute other code here. Block cache operations proceed in parallel with CPU
execution, stalling CPU minimally. */
/* ---------------------------------------------------- */
/* . . . */
/* ---------------------------------------------------- */
/* Now, spin waiting for operation to complete. */
/* ---------------------------------------------------- */
while (L2WWC != 0)
;
To ensure write-back completion of a specific buffer (contiguous address range), see Section 5.4.3.4.6 ,
Write-Back Completion, for additional programming steps and an example.
• Block write-back and invalidate
Block write-back and invalidate is controlled by the following registers: IVA_XMC.
L2WIBAR ,
IVA_XMC. L2WIWC , IVA_XMC. L1DWIBAR , and IVA_XMC. L1DWIWC .
Example of block write-back and invalidate:
/* ---------------------------------------------------- */
/* Write base address of array to Base Address Register.*/
/* Then write length of array, in words, to the Word */
/* Count register. */
/* ---------------------------------------------------- */
L2WIBAR = &array[0];
L2WIWC = (array) / sizeof(int);
/* . . . */
/* ---------------------------------------------------- */
/*The CPU can execute other code here. Block cache operations proceed in parallel with CPU
execution, stalling the CPU minimally. */
/* ---------------------------------------------------- */
/* . . . */
/* ---------------------------------------------------- */
/* Now, spin waiting for operation to complete. */
/* ---------------------------------------------------- */
while (L2WIWC != 0)
;
To ensure write-back completion of a specific buffer (contiguous address range), see Section 5.4.3.4.6
for additional programming steps and an example.
5.4.3.4.6 Write-Back Completion
The SYSC_LICFG0 [15] GEMTRUECOMPEN bit must be set to 1 before any DSP CPU C64x+ write for
which completion must be ensured. This applies to writes to noncacheable regions and to cache-line
write-back completions. By default,
SYSC_LICFG0 [15] GEMTRUECOMPEN = 0. This default is
recommended, to statically set that bit (unless the user wants to locally send a large number of writes to a
noncacheable memory region):
• SYSC_LICFG0 .GEMTRUECOMPEN = 1;
Polling on the L*WWC (resp. L*WIWC) ensures that the block write-back operation (and associated
invalidate, when applicable) was completely issued by the associated cache controller, but does not
ensure that the write-back is effective in end memory.
To get completion of the write-back of a specific buffer after block or global cache write-back, the user
must read back from a noncacheable region of the same L3 or L4 target as the buffer (if data is written
in external DDR memory, the read access can be on an SDRC register). The C64x + is uninstalled
only after the read following the write-back is complete.
755 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated