Texas Instruments OMAP36 Series, Technical Reference Manual

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SDMA Basic Programming Model
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11.5 SDMA Basic Programming Model
11.5.1 Setup Configuration
After a hardware reset, program all fields in the logical channel registers to default values for any channels
used, because most fields are undefined following reset.
Before programming any DMA transfers, the priority arbitration rate and the maximum FIFO depth must be
configured through the
DMA4_GCR register, and any required interrupts must be enabled through the
DMA4_IRQENABLE_Lj registers and the logical channel DMA4_CICRi registers.
Software clears the DMA4_CSRi register and the IRQSTATUS bit for the different interrupt lines before
enabling the channel.
11.5.2 Software-Triggered (Nonsynchronized) Transfer
To program a software-triggered DMA transfer:
1. Configure the transfer parameters in the logical DMA channel registers:
• DMA4_CSDPi :
– Transfer ES (8 bits, 16 bits, or 32 bits) and DMA register bits DMA4_CSDPi [1:0]
– Read and write port access types (single/burst), DMA register bits DMA4_CSDPi [8:7] and
DMA4_CSDPi [15:14]
– Source and destination endianism, DMA register bits DMA4_CSDPi [21] and DMA4_CSDPi [19]
– Write mode (posted or nonposted) and DMA register bits DMA4_CSDPi [17:16]
– Source or destination packed or nonpacked (if the ES is less than the read/write port size),
DMA register bits
DMA4_CSDPi [6] and DMA4_CSDPi [13]
• DMA4_CENi : EN
• DMA4_CFNi : FN per transfer block
• DMA4_CSSAi and DMA4_CDSAi : Source and destination start address (aligned with transfer ES)
• DMA4_CCRi :
– Read and write port addressing modes, DMA register bits DMA4_CCRi [13:12] and
DMA4_CCRi [15:14]
– Priority bit for both read and write ports, DMA register bits DMA4_CCRi [6] and DMA4_CCRi [26]
– DMA request number (set to 0 for a software-triggered transfer) and DMA register bits
DMA4_CCRi [4:0] = 0 and DMA4_CCRi [20:19] = 0
• DMA4_CSEi, DMA4_CSFi, DMA4_CDEi, and DMA4_CDFi: Source and destination element and
frame indexes (depending on addressing mode)
2. Start the transfer through the enable bit in the channel DMA4_CCRi register and DMA register bit
DMA4_CCRi [7]
The example below perform a DMA transfer on channel 10 of a 240*160 picture from RAM to RAM
(0x80C00000 to 0x80F00000) :
UWORD32 RegVal = 0; DMA4_t *DMA4; DMA4 = (DMA4_t *)malloc(sizeof(DMA4_t)); /* Init. parameters
*/ DMA4->DataType = 0x2; // DMA4_CSDPi[1:0] DMA4->ReadPortAccessType = 0; // DMA4_CSDPi[8:7] DMA4-
>WritePortAccessType = 0; // DMA4_CSDPi[15:14] DMA4->SourceEndiansim = 0; // DMA4_CSDPi[21] DMA4-
>DestinationEndianism = 0; // DMA4_CSDPi[19] DMA4->WriteMode = 0; // DMA4_CSDPi[17:16] DMA4-
>SourcePacked = 0; // DMA4_CSDPi[6] DMA4->DestinationPacked = 0; // DMA4_CSDPi[13] DMA4-
>NumberOfElementPerFrame = 240; // DMA4_CENi DMA4->NumberOfFramePerTransferBlock = 160; //
DMA4_CFNi DMA4->SourceStartAddress = 0x80C00000; // DMA4_CSSAi DMA4->DestinationStartAddress =
0x80F00000; // DMA4_CDSAi DMA4->SourceElementIndex = 1; // DMA4_CSEi DMA4->SourceFrameIndex = 1;
// DMA4_CSFi DMA4->DestinationElementIndex = 1; // DMA4_CDEi DMA4->DestinationFrameIndex = 1; //
DMA4_CDFi DMA4->ReadPortAccessMode = 1; // DMA4_CCRi[13:12] DMA4->WritePortAccessMode = 1; //
DMA4_CCRi[15:14] DMA4->ReadPriority = 0; // DMA4_CCRi[6] DMA4->WritePriority = 0; //
DMA4_CCRi[23] DMA4->ReadRequestNumber = 0; // DMA4_CCRi[4:0] DMA4->WriteRequestNumber = 0; //
DMA4_CCRi[20:19] /* 1) Configure the transfer parametres in the logical DMA registers */ /*-------
------------------------------------------------------------*/ /* a) Set the data type CSDP[1:0],
the Read/Write Port access type CSDP[8:7]/[15:14], the Source/dest endiansim CSDP[21]/CSDP[19],
write mode CSDP[17:16], source/dest packed or non-packed CSDP[6]/CSDP[13]*/ // Read CSDP RegVal =
DMA4_CSDP_CH10; // Build reg RegVal = ((RegVal & ~ 0x3) | DMA4->DataType ); RegVal = ((RegVal &
~(0x3 << 7)) | (DMA4->ReadPortAccessType << 7)); RegVal = ((RegVal & ~(0x3 << 14)) | (DMA4-
>WritePortAccessType << 14)); RegVal = ((RegVal & ~(0x1 << 21)) | (DMA4->SourceEndiansim << 21));
RegVal = ((RegVal & ~(0x1 << 19)) | (DMA4->DestinationEndianism << 19)); RegVal = ((RegVal &
~(0x3 << 16)) | (DMA4->WriteMode << 16)); RegVal = ((RegVal & ~(0x1 << 6)) | (DMA4->SourcePacked
2368 SDMA SWPU177N – December 2009 – Revised November 2010
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