MSP430xG461x
MIXED SIGNAL MICROCONTROLLER
SLAS508I − APRIL 2006 − REVISED MARCH 2011
48
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (I2C mode) (see Figure 22)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
f
USCI
USCI input clock frequency
Internal: SMCLK, ACLK
External: UCLK
Duty Cycle = 50%
±
10%
f
SYSTEM
MHz
f
SCL
SCL clock frequency
2.2 V/3 V
0
400
kHz
t
Hold time (repeated) START
f
SCL
≤
100kHz
2.2 V/3 V
4.0
s
t
HD,STA
Hold time (repeated) START
f
SCL
> 100kHz
2.2 V/3 V
0.6
μ
s
t
Set up time for a repeated START
f
SCL
≤
100kHz
2.2 V/3 V
4.7
s
t
SU,STA
Set−up time for a repeated START
f
SCL
> 100kHz
2.2 V/3 V
0.6
μ
s
t
HD,DAT
Data hold time
2.2 V/3 V
0
ns
t
SU,DAT
Data set−up time
2.2 V/3 V
250
ns
t
SU,STO
Set−up time for STOP
2.2 V/3 V
4.0
μ
s
t
Pulse width of spikes suppressed by
2.2 V
50
150
600
ns
t
SP
Pulse width of spikes suppressed by
input filter
3 V
50
100
600
ns
SDA
SCL
t
LOW
t
HD ,DAT
t
SU ,DAT
t
HD , STA
t
SU , STA
t
HD , STA
t
HIGH
t
SU , STO
t
SP
t
BUF
Figure 22. I2C Mode Timing
USART1 (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
USART1 deglitch time
V
CC
= 2.2 V, SYNC = 0, UART mode
200
430
800
ns
t
(
τ
)
USART1 deglitch time
V
CC
= 3 V, SYNC = 0, UART mode
150
280
500
ns
NOTE 1: The signal applied to the USART1 receive signal/terminal (URXD1) should meet the timing requirements of t
(τ
)
to ensure that the URXS
flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t
(τ
)
. The operating conditions to
set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the
URXD1 line.
Summary of Contents for MSP430CG4616IPZ
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