Texas Instruments Jacinto 7 DRA829, User Manual

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7 Application Examples
This section provides examples of how to interact with the PMICs from the perspective of the MCU and over I
2
C.
Table 7-1 shows how the I
2
C commands are presented in the following sections. These examples, when used in
conjunction with the datasheet , can be generalized and applied to other use cases.
Table 7-1. I
2
C Instruction Format
I2C Address Register Address Data Mask
0x48 or 0x4C 0x00 - 0xFF 0x00 - 0xFF 0x00 - 0xFF
7.1 Moving Between States; ACTIVE, MCU ONLY, and RETENTION
The default configuration of the NVM transitions the PMICs to the ACTIVE state when the ENABLE pin on
the TPS65941213 goes high (rising edge triggered). The nINT pin goes high to indicate to the MCU that
interrupts have occurred in the PMICs. After a normal power up sequence the interrupts are the ENABLE_INT
and BIST_PASS_INT. The ENABLE_INT prohibits the PMICs from processing any lower priority triggers below
the 'ON Request' in
Table 6-1 . This is why the PMICs are in the ACTIVE state even though the NSLEEP1
and NSLEEP2 bits are both cleared. Once the ENABLE_INT is cleared the state is defined by Table 7-2 . The
following sections describe the I
2
C commands for transitioning between the different states.
Table 7-2. State Table
NSLEEP1 NSLEEP2 I2C_7 I2C_6 State
1 1 NA NA ACTIVE
0 1 1 NA MCU Only with DDR
Retention
0 1 0 NA MCU Only without DDR
Retention
Do not Care 0 1 NA DDR Retention
0 0 NA Retention
7.1.1 ACTIVE
In this example the, PMIC is already in the ACTIVE state after a normal power up event. The PMIC is kept in the
ACTIVE state by setting the NSLEEP1 and NSLEEP2 bits before clearing the ENABLE_INT.
Write 0x48:0x86:0x03:0xFC // Set NSLEEP1 and NSLEEP2 in TPS65951213
Write 0x48:0x66:0x01:0xFE // Clear BIST_PASS_INT
Write 0x48:0x65:0x26:0xD9 // Clear all potential sources of the On Request
7.1.2 MCU ONLY
Transitioning to the MCU ONLY state from the ACTIVE state, requires configuring the I2C_7 trigger before
changing the NSLEEP bits. The configuration must be consistent between both PMICs.
Write 0x48:0x85:0x80:0x7F // Set I2C_7 Trigger on TPS65941213
Write 0x4C:0x85:0x80:0x7F // Set I2C_7 Trigger on TPS65941111
Write 0x48:0x86:0x02:0xFC // Set NSLEEP2 to trigger TO_MCU power sequence
Instead of writing to the NSLEEP bits to return to the ACTIVE state, it is also possible to use the WKUP1 pin on
GPIO4 or GPIO10 to return the PMIC to the ACTIVE state. Because of the similarity this is shown in the context
of the RETENTION state.
7.1.3 RETENTION
As shown in Section 6.3.9 , the MCU is powered off and therefore the transition out of the RETENTION
to the MCU ONLY or the ACTIVE states must be configured before entering RETENTION. Similar to the
MCU ONLY state the I2C_7 triggers must be set for both PMICs. Additionally, the TPS65941111 GPIO4
Application Examples www.ti.com
50 Optimized Dual TPS6594-Q1 PMIC User Guide for Jacinto ™ 7 DRA829 or
TDA4VM Automotive PDN-0C
SLVUC99 – JANUARY 2022
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