The TO_SAFE_SEVERE sequence executes the following instruction after the power sequence:
//TPS65941213 and TPS65941111
// Clear AMUXOUT_EN, CLKMON_EN, set LPM_EN
REG_WRITE_MASK_IMM ADDR=0x81 DATA=0x04 MASK=0xE3
The TPS65941213 has an additional delay of 500 ms at the end of the TO_SAFE_SEVERE sequence. It is
important to note that the recovery is not attempted until after the sequence delay is complete.
6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
If a moderate error occurs, an orderly shutdown trigger is generated. This trigger shuts down the PMIC outputs
using the recommended power down sequence and proceed to the SAFE state.
If an OFF request occurs, such as the ENABLE pin of the primary TPS6594-Q1 device being pulled low,
the same power down sequence occurs, except that the PMICs go to STANDBY (LP_STANDBY_SEL=0) or
LP_STANDBY (LP_STANDBY_SEL=1) states, rather than going to the SAFE state. The power sequence for
both of these events is shown in
.
Both the TO_SAFE_ORDERLY and TO_STANDBY sequences set the SPMI_LP_EN and
FORCE_EN_DRV_LOW in the TPS65941213 while only the SPMI_LP_EN is set in the TPS65941111.
Pre-Configurable Finite State Machine (PFSM) Settings
SLVUC99 – JANUARY 2022
Optimized Dual TPS6594-Q1 PMIC User Guide for Jacinto
™
7 DRA829 or
TDA4VM Automotive PDN-0C
37
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