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5.12 Multi-Device Settings

These settings detail whether the device is a operating as a primary or secondary in the system. These settings
cannot be changed after device startup.

Table 5-12. Multi-Device NVM Settings

Register Name

Field Name

TPS65941213-Q1

TPS65941111-Q1

Value

Description

Value

Description

SPMI_CONFIG_1

SPMI_CRC_EN

0x1

SPMI CRC check enabled

0x1

SPMI CRC check enabled

BIT 1

0x1

Primary mode

0x0

Secondary mode

SPMI_CLK_SEL

0x2

5MHz

0x2

5MHz

SPMI_CONFIG_2

SPMI_IF_SEL

0x0

Debug feature and uses
primary logic to implement
logical secondary.

0x0

Debug feature and uses
primary logic to implement
logical secondary.

SPMI_RETRY_LIMIT

0x3

Three retries in case of error
detected

0x3

Three retries in case of error
detected

SPMI_WD_AUTO_BOO
T

0x1

SPMI auto boot enabled

0x1

SPMI auto boot enabled

SPMI_EN

0x1

SPMI enabled

0x1

SPMI enabled

SPMI_WD_EN

0x1

SPMI WD enabled

0x1

SPMI WD enabled

SPMI_CONFIG_3

SPMI_WD_BOOT_
INTERVAL

0x8

SPMI_WD_RUNTIME_
INTERVAL

0x8

SPMI_CONFIG_4

SPMI_WD_RESPONSE
_ TIMEOUT

0x8

SPMI_PFSM_RESPON
SE_ TIMEOUT

0x8

SPMI_CONFIG_5

SPMI_WD_RUNTIME_
BIST_ TIMEOUT

0x8

SPMI_WD_BOOT_BIS
T_ TIMEOUT

0x8

SPMI_CONFIG_6

BOOT_DELAY

0x0

SPMI_ID

SPMI_SID

0x5

0x3

SPMI_MID

0x0

5.13 Watchdog Settings

These settings detail the default watchdog addresses. These settings can be changed though I

C after startup.

Table 5-13. Watchdog NVM Settings

Register Name

Field Name

TPS65941213-Q1

TPS65941111-Q1

Value

Description

Value

Description

WD_LONGWIN_CFG

WD_LONGWIN

0xff

WD_THR_CFG

WD_EN

0x1

Watchdog enabled.

0x0

Watchdog disabled.

6 Pre-Configurable Finite State Machine (PFSM) Settings

This section describes the default PFSM settings of the TPS6594-Q1 devices. These settings cannot be
changed after device startup.

Static NVM Settings

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Optimized Dual TPS6594-Q1 PMIC User Guide for Jacinto

™

7 DRA829 or

TDA4VM Automotive PDN-0C

SLVUC99 – JANUARY 2022

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Summary of Contents for Jacinto 7 DRA829

Page 1: ... Settings 21 5 6 GPIO Settings 21 5 7 Finite State Machine FSM Settings 23 5 8 Interrupt Settings 24 5 9 POWERGOOD Settings 27 5 10 Miscellaneous Settings 28 5 11 Interface Settings 29 5 12 Multi Device Settings 30 5 13 Watchdog Settings 30 6 Pre Configurable Finite State Machine PFSM Settings 30 6 1 Configured States 31 6 2 PFSM Triggers 33 6 3 Power Sequences 35 7 Application Examples 50 7 1 Mov...

Page 2: ...PMIC sequencing settings to support different PDN power state transitions for an advanced processor system PMIC and processor data manuals provide recommended operating conditions electrical characteristics recommended external components package details register maps and overall component functionality In the event of any inconsistency between any user s guide application report or other referenc...

Page 3: ...s Supports I O level of 3 3 V or 1 8 V Supports optional end product features Compliant high speed SD Card memory Compliant USB 2 0 Interface On board Efuse programming of high security processors 0C 3 TPS65941213 RWERQ1 0x13 0x04 TPS65941111 RWERQ1 0x11 0x03 Dedicated MCU and SOC 0B TPS65941212 RWERQ1 0x12 0x03 TPS65941111 RWERQ1 0x11 0x03 Combined MCU and SOC 1 TI recommends having 15 margin bet...

Page 4: ...ted 3 3 V to processor I O domains Two load switches are required in order to enable isolation between MCU and Main processor sub sections for MCU Safety Island or MCU Only low power operations The unused feedback pin FB_B3 of the TPS65941213 has been configured per NVM settings Table 5 3 to provide voltage monitoring for VDD_MCUIO_3V3_LS power rail This enables all of the MCU processor power supp...

Page 5: ...4A max LDO1 500mA max LDO2 500mA max LDO3 500mA max LDO4 300mA max BUCK5 4A max VSYS_3V3 OVPGDRV VDDA_1P8_PHYs MAIN ANALOG VDDA_0P8_PHYs VDDA_0P8_PLLs DLLs VDDA_1P8_PLLs VDDA_3P3_USB VDDSHV0 4 MAIN DIGITAL VDDSHV6 VDDSHV5 VDDS_MMC0 VPP_x EFUSE Octal SPI FLASH Hyper FLASH EMMC VCCQ VCC UFS VCCQ VCC VDD_CPU_AVS FB_B3 pin 49 VDD_MCU_0V85 VDD_PHY_1V8 VDD_MCUIO_1V8 VDA_MCU_1V8 VDD_DDR_1V1 VDD1_LPDDR_1V...

Page 6: ...MCUI O_1V8 VDDSHVx_MCU 1 8 V R R Mem VCC LDO3 VDA_DLL_0 V8 VDDA_0P8_PLLs DLLs R LDO4 VDA_MCU_ 1V8 VDDA_x R R TPS659411 11 Q1 BUCK1234 VDD_CORE _0V8 VDD_CORE VDDA_0P8_PHYs R BUCK5 VDD_RAM_ 0V85 VDDAR_CPU CORE R LDO1 VDD_SD_D V VDDSHV5 R LDO2 VDD_USB_ 3V3 VDDA_3P3_USB R LDO3 VDD_IO_1V 8 VDDS_MMC0 R Mem VCCQ LDO4 VDA_PLL_1 V8 VDDA_1P8_PLLs R TPS22965 Q1 Load Switch VDD_MCUI O_3V3 VDDSHVx_MCU 3 3 V R ...

Page 7: ... PMIC in order to correctly initiate the PFSM Other digital connections from the TPS6594 Q1 PMICs to the processor provide error monitoring processor reset processor wake up and system low power modes Specific GPIO pins have been assigned to key signals in order to ensure proper operation during low power modes when only a few GPIO pins remain operational The digital connections shown in Figure 3 ...

Page 8: ...e12 PMIC_Wake2 H_MCU_INTn_3V3 H_MCU_PORz_1V8 H_MCU_I2C0 H_WKUP_I2C0 H_SOC_SAFETY_ERRn PMIC_WAKE13 H_MCU_SAFETY_ERRn PMIC_GPIO8 EN_MCU3V3IO_LDSW PMIC_GPIO103 H_SOC_PORz_1V8 PMICA_SCLK PMICA_SDATA SEL_SDIO_3V3_1V8n EN_VDDR H_DDR_RET_1V1 EN_EFUSE_VPP PMIC_WAKE23 EN_3V3IO_LDSW Power Processor Group Processor Sub group Processor Supply Groups System Group System IO Domain Descriptors VCCA VRTC 1 8V VIN...

Page 9: ...1V8 VDA_MCU_1V8 H_SOC_PORz_1V8 VDA_MCU_1V8 H_DDR_RET_1V1 VDD_DDR_1V1_REG H_WKUP_I2C0 VDD_MCUIO_3V3 H_MCU_I2C0_SCL SDA VDD_MCUIO_3V3 Please use Table 3 3 as a guide to understand GPIO assignments required for each PDN system feature If the feature listed is not required the digital connection can be removed however the GPIO pin is still configured per NVM defined default function shown After the pr...

Page 10: ...IC_PWR_EN1 R GPIO_11 nRSTOUT_ SOC H_SOC_PORz_1V8 R TPS659411 11 Q1 nPWRON ENABLE ENABLE VINT_LEOA_1V8 R nINT nINT H_MCU_INTn nRSTOUT nRSTOUT Unused SCL_I2C1 SCL_I2C1 H_WKUP_I2C0 R SDA_I2C1 SCL_I2C1 H_WKUP_I2C0 R GPIO_1 GPI Unused 5 GPIO_2 GPI SEL_SDIO_3V3_1V8n 3 R GPIO_3 GPO EN_DDR_BUCK R O R GPIO_4 6 GPO H_DDR_RET_1V1 R GPIO_5 SCLK_SPM I LEOA_SCLK R GPIO_6 SDATA_SP MI LEOA_SDATA R GPIO_7 GPI Unus...

Page 11: ...e following PMIC functional safety features Independent Power Control of MCU and Main Rails Independent Monitoring and Reset for MCU and Main Rails Input Supply Monitoring Output Voltage and Current Monitoring Question and Answer Watchdog Fault Reporting Interrupts Enable Drive Pin that provides an independent path to disable system actuators Error Pin Monitoring Internal Diagnostics including vol...

Page 12: ... Section 7 4 The internal Q A Watchdog is enabled on the primary TPS6594 Q1 device Once the device is in ACTIVE state the trigger or Q A watchdog settings can be configured through the secondary I2C in the device The primary and secondary I2C CRC is not enabled by default but must be enabled with the I2C_2 trigger described in section Table 6 1 Once enabled the secondary I2C is disabled for 2ms It...

Page 13: ...he primary PMIC www ti com Supporting Functional Safety Systems SLVUC99 JANUARY 2022 Submit Document Feedback Optimized Dual TPS6594 Q1 PMIC User Guide for Jacinto 7 DRA829 or TDA4VM Automotive PDN 0C 13 Copyright 2022 Texas Instruments Incorporated ...

Page 14: ...Watchdog and I2C2 PMICA1 and PMICB2 nINT PMICA nERR_MCU connected to SOC MCU_SAF ETY_ERRz PMICA nRSTOUT connected to MCU_PORz_1 V8 PMICA ENDRV PMICA VSYS_SENSE OV with Safety FET OVPGDRV PMICA and PMICB with VCCA OV UV and SoC VMON1 UV PMICA nERR_SoC connected to SOC SOC_SAFETY_ ERRz PMICA nINT nRSTOUT nRSTOUT_SO C PMICB nINT 1 PMICA TPS65941213 Q1 2 PMICB TPS65941111 Q1 Table 4 2 Power Monitoring...

Page 15: ...MIC monitor is associated with the MCU power group and can be updated during run time 6 Power rail VPP_EFUSE_1V8 is not safety critical since Efuse programming does not occur during safety critical processing 7 PMIC B Buck3 and 4 have unused remote sense feedback inputs that can be assigned to provide OV and UV voltage monitoring after SoC SW boot for 2x external power rails per desired functional...

Page 16: ...9 V Multiphase or Single Phase 470 nH BUCK4 2 2 MHz VOUT Less than 1 9 V Multiphase or Single Phase 470 nH BUCK5 2 2 MHz VOUT Less than 1 9 V Multiphase or Single Phase 470 nH TPS65941111 Q1 BUCK1 2 2 MHz VOUT Less than 1 9 V Multiphase or Single Phase 470 nH BUCK2 2 2 MHz VOUT Less than 1 9 V Multiphase or Single Phase 470 nH BUCK3 2 2 MHz VOUT Less than 1 9 V Multiphase or Single Phase 470 nH BU...

Page 17: ...d Name TPS65941213 Q1 TPS65941111 Q1 Value Description Value Description BUCK1_CTRL BUCK1_EN 0x0 Disabled BUCK1 regulator 0x0 Disabled BUCK1 regulator BUCK1_FPWM 0x0 PFM and PWM operation AUTO mode 0x0 PFM and PWM operation AUTO mode BUCK1_FPWM_MP 0x0 Automatic phase adding and shedding 0x0 Automatic phase adding and shedding BUCK1_VMON_EN 0x0 Disabled OV UV SC and ILIM comparators 0x0 Disabled OV...

Page 18: ...x0 Disabled BUCK5 regulator 0x0 Disabled BUCK5 regulator BUCK5_FPWM 0x0 PFM and PWM operation AUTO mode 0x0 PFM and PWM operation AUTO mode BUCK5_VMON_EN 0x0 Disabled OV UV SC and ILIM comparators 0x0 Disabled OV UV SC and ILIM comparators BUCK5_VSEL 0x0 BUCK5_VOUT_1 0x0 BUCK5_VOUT_1 BUCK5_PLDN 0x1 Enable Pull down resistor 0x1 Enable Pull down resistor BUCK5_RV_SEL 0x1 Enabled 0x1 Enabled BUCK5_C...

Page 19: ... 5 50 mV 0x0 3 30mV BUCK4_UV_THR 0x3 5 50 mV 0x0 3 30mV BUCK5_PG_WINDOW BUCK5_OV_THR 0x3 5 50 mV 0x3 5 50 mV BUCK5_UV_THR 0x3 5 50 mV 0x3 5 50 mV www ti com Static NVM Settings SLVUC99 JANUARY 2022 Submit Document Feedback Optimized Dual TPS6594 Q1 PMIC User Guide for Jacinto 7 DRA829 or TDA4VM Automotive PDN 0C 19 Copyright 2022 Texas Instruments Incorporated ...

Page 20: ...N 0x0 Disabled LDO3 regulator 0x0 Disabled LDO3 regulator LDO3_SLOW_RA MP 0x0 25mV us max ramp up slew rate for LDO output from 0 3V to 90 of LDOn_VSET 0x0 25mV us max ramp up slew rate for LDO output from 0 3V to 90 of LDOn_VSET LDO3_PLDN 0x1 125 Ohm 0x1 125 Ohm LDO3_VMON_EN 0x0 Disabled OV and UV comparators 0x0 Disabled OV and UV comparators LDO3_RV_SEL 0x1 Enabled 0x1 Enabled LDO4_CTRL LDO4_EN...

Page 21: ...EL field determine which other fields in the GPIOx_CONF and GPIO_OUT_x registers are applicable To understand which NVM fields apply to each GPIOx_SEL option see the Digital Signal Descriptions section in TPS6594 Q1 data sheet Table 5 6 GPIO NVM Settings Register Name Field Name TPS65941213 Q1 TPS65941111 Q1 Value Description Value Description GPIO1_CONF GPIO1_OD 0x0 Push pull output 0x0 Push pull...

Page 22: ...No deglitch only synchronization 0x0 No deglitch only synchronization GPIO6_CONF GPIO6_OD 0x0 Push pull output 0x0 Push pull output GPIO6_DIR 0x0 Input 0x0 Input GPIO6_SEL 0x1 SDATA_SPMI 0x1 SDATA_SPMI GPIO6_PU_SEL 0x0 Pull down resistor selected 0x0 Pull down resistor selected GPIO6_PU_PD_EN 0x1 Enabled Pull up pull down resistor 0x0 Disabled Pull up pull down resistor GPIO6_DEGLITCH_EN 0x0 No de...

Page 23: ... up pull down resistor GPIO11_DEGLITCH_E N 0x0 No deglitch only synchronization 0x0 No deglitch only synchronization NPWRON_CONF NPWRON_SEL 0x0 ENABLE 0x0 ENABLE ENABLE_PU_SEL 0x0 Pull down resistor selected 0x0 Pull down resistor selected ENABLE_PU_PD_EN 0x1 Enabled Pull up pull down resistor 0x1 Enabled Pull up pull down resistor ENABLE_DEGLITCH_E N 0x1 8 us deglitch time when ENABLE 50 ms degli...

Page 24: ...ield Name TPS65941213 Q1 TPS65941111 Q1 Value Description Value Description FSM_TRIG_MASK_1 GPIO1_FSM_MASK 0x1 Masked 0x1 Masked GPIO1_FSM_MASK_P OL 0x0 Low Masking sets signal value to 0 0x0 Low Masking sets signal value to 0 GPIO2_FSM_MASK 0x1 Masked 0x0 Not masked GPIO2_FSM_MASK_P OL 0x0 Low Masking sets signal value to 0 0x0 Low Masking sets signal value to 0 GPIO3_FSM_MASK 0x1 Masked 0x1 Mask...

Page 25: ...generated MASK_LDO1_2 LDO1_OV_MASK 0x0 Interrupt generated 0x0 Interrupt generated LDO1_UV_MASK 0x0 Interrupt generated 0x0 Interrupt generated LDO2_OV_MASK 0x0 Interrupt generated 0x0 Interrupt generated LDO2_UV_MASK 0x0 Interrupt generated 0x0 Interrupt generated LDO1_ILIM_MASK 0x0 Interrupt generated 0x0 Interrupt generated LDO2_ILIM_MASK 0x0 Interrupt generated 0x0 Interrupt generated MASK_LDO...

Page 26: ...ARTUP NPWRON_START_MA SK 0x1 Interrupt not generated 0x1 Interrupt not generated ENABLE_MASK 0x0 Interrupt generated 0x0 Interrupt generated FSD_MASK 0x1 Interrupt not generated 0x1 Interrupt not generated SOFT_REBOOT_MAS K 0x0 Interrupt generated 0x0 Interrupt generated MASK_MISC TWARN_MASK 0x0 Interrupt generated 0x0 Interrupt generated BIST_PASS_MASK 0x0 Interrupt generated 0x0 Interrupt genera...

Page 27: ...nerated 0x1 Interrupt not generated ESM_MCU_FAIL_MAS K 0x1 Interrupt not generated 0x1 Interrupt not generated GENERAL_REG_1 PFSM_ERR_MASK 0x0 Interrupt generated 0x0 Interrupt generated 1 The VCCA_OV_MASK and VCCA_UV_MASK are cleared in both PMICs after the completing BOOT_BIST but before starting the sequence Section 6 3 8 5 9 POWERGOOD Settings These settings detail the default configurations f...

Page 28: ...de controller code I2C2_HS 0x0 Standard fast or fast by default can be set to Hs mode by Hs mode controller code 0x0 Standard fast or fast by default can be set to Hs mode by Hs mode controller code EN_ILIM_FSM_CTRL 0x0 Buck LDO regulators ILIM interrupts do not affect FSM triggers 0x0 Buck LDO regulators ILIM interrupts do not affect FSM triggers NSLEEP1_MASK 0x0 NSLEEP1 B affects FSM state trans...

Page 29: ...ndby state LDOINT is disabled FAST_BIST 0x0 Logic and analog BIST is run at BOOT BIST 0x0 Logic and analog BIST is run at BOOT BIST STARTUP_DEST 0x3 ACTIVE 0x3 ACTIVE XTAL_SEL 0x0 6 pF 0x0 6 pF PFSM_DELAY_REG_1 PFSM_DELAY1 0x58 0x58 0x0 0x0 PFSM_DELAY_REG_2 PFSM_DELAY2 0x9d 0x9d 0x1d 0x1d PFSM_DELAY_REG_3 PFSM_DELAY3 0x0 0x0 0x0 0x0 PFSM_DELAY_REG_4 PFSM_DELAY4 0x0 0x0 0x0 0x0 GENERAL_REG_0 FAST_B...

Page 30: ...TERVAL 0x8 0x8 0x8 0x8 SPMI_WD_RUNTIME_ INTERVAL 0x8 0x8 0x8 0x8 SPMI_CONFIG_4 SPMI_WD_RESPONSE _ TIMEOUT 0x8 0x8 0x8 0x8 SPMI_PFSM_RESPON SE_ TIMEOUT 0x8 0x8 0x8 0x8 SPMI_CONFIG_5 SPMI_WD_RUNTIME_ BIST_ TIMEOUT 0x8 0x8 0x8 0x8 SPMI_WD_BOOT_BIS T_ TIMEOUT 0x8 0x8 0x8 0x8 SPMI_CONFIG_6 BOOT_DELAY 0x0 0x0 0x0 0x0 SPMI_ID SPMI_SID 0x5 0x5 0x3 0x3 SPMI_MID 0x0 0x0 0x0 0x0 5 13 Watchdog Settings These ...

Page 31: ...tionally the transitions to hardware states such as SAFE RECOVERY and LP_STANDBY are shown The hardware states are part of the fixed device power Finite State Machine FSM and described in the TPS6594 Q1 data sheet see Section 8 www ti com Pre Configurable Finite State Machine PFSM Settings SLVUC99 JANUARY 2022 Submit Document Feedback Optimized Dual TPS6594 Q1 PMIC User Guide for Jacinto 7 DRA829 ...

Page 32: ... 1 0 11b OFF Request Warm Reset triggered by ESM SOC or WatchDog Error Warm Reset triggered by MCU SOC or WatchDog Error DDR Retention DDR From any PFSM State Valid Wake Request Pwr SOC Error DDR SOC Power Error B Figure 6 1 Pre Configurable Finite State Machine PFSM Mission States and Transitions When the PMICs transition from the FSM to the PFSM several initialization instructions are performed ...

Page 33: ...e The return to MCU_ONLY mode and eventually ACTIVE mode is only recommended after the interrupts which caused the SOC_PWR_ERROR have been cleared Retention The PMICs are powered by a valid supply When the PMICs I2C_7 triggers are set DDR Retention only 3 SoC voltage domains vdds_ddr_bias vdds_ddr and vdds_ddr_c remain energized while all other domains are off to minimize total system power EN_DRV...

Page 34: ...False ACTIVE MCU ONLY No State Change Devices are prepared for OTA NVM update 6 1 From the SAFE state the PFSM automatically transitions to the hardware FSM state of SAFE_RECOVERY From the SAFE_RECOVERY state the recovery counter is incremented and compared to the recovery count threshold see RECOV_CNT_REG_2 in Table 5 10 If the recovery count threshold is reached then the PMICs halt recovery atte...

Page 35: ...ces These triggers are used to manage the transition between the PFSM and the FSM 6 3 Power Sequences 6 3 1 TO_SAFE_SEVERE and TO_SAFE The TO_SAFE_SEVERE and TO_SAFE are distinct sequences which occur when transition to the SAFE state Both sequences shut down all rails without delay The TO_SAFE_SEVERE sequence immediately ceases BUCK switching and enables the pulldown resistors of the BUCKs and LD...

Page 36: ...PS65941111 Q1 0 us VDD_SD_DV LDO2 TPS65941111 Q1 0 us VDD_USB_3V3 GPIO11 TPS65941111 Q1 0 us EN_3V3IO_LDSW EN_DRV TPS65941213 Q1 0 us EN_DRV Figure 6 2 TO_SAFE_SEVERE and TO_SAFE Power Sequences After the power sequence shown in Figure 6 2 the TO_SAFE sequence delays the TPS65941213 by 16 ms and the TPS65941111 by 3 ms This ensures that the primary PMIC finishes after the secondary After these del...

Page 37: ... sequence and proceed to the SAFE state If an OFF request occurs such as the ENABLE pin of the primary TPS6594 Q1 device being pulled low the same power down sequence occurs except that the PMICs go to STANDBY LP_STANDBY_SEL 0 or LP_STANDBY LP_STANDBY_SEL 1 states rather than going to the SAFE state The power sequence for both of these events is shown in Figure 6 3 Both the TO_SAFE_ORDERLY and TO_...

Page 38: ...500 us VDD_CORE_0V8 LDO4 TPS65941111 Q1 3000 us VDA_PLL_1V8 LDO1 TPS65941111 Q1 3500 us VDD_SD_DV LDO2 TPS65941111 Q1 3500 us VDD_USB_3V3 GPIO11 TPS65941111 Q1 3500 us EN_3V3IO_LDSW EN_DRV TPS65941213 Q1 0 us EN_DRV Figure 6 3 TO_SAFE_ORDERLY and TO_STANDBY Power Sequence At the end of the TO_SAFE_ORDERLY both PMICs wait approximately 16 ms before executing the following instructions TPS65941213 C...

Page 39: ..._REG_1 increments Then all BUCKs and LDOs are reset to their default voltages The PMICs remain in the ACTIVE state Note GPIOs do not reset during the sequence as shown in Figure 6 4 At the beginning of the sequence the following instructions are executed TPS65941213 Set FORCE_EN_DRV_LOW REG_WRITE_MASK_IMM ADDR 0x82 DATA 0x08 MASK 0xF7 Clear nRSTOUT and nRSTOUT_SOC REG_WRITE_MASK_IMM ADDR 0x81 DATA...

Page 40: ...TPS65941213 Q1 2000 us H_MCU_PORz_1V8 nRSTOUT_SOC TPS65941213 Q1 2000 us H_SOC_PORz_1V8 EN_DRV TPS65941213 Q1 0 us EN_DRV Figure 6 4 ACTIVE_TO_WARM Power Sequence Note The regulator transitions do not represent enabling of the regulators but the time at which the voltages are restored to their default values Since this sequence originates from the ACTIVE state all of the regulators are on 6 3 4 ES...

Page 41: ... ADDR 0x81 DATA 0x18 MASK 0xE1 Clear SPMI_LPM_EN REG_WRITE_MASK_IMM ADDR 0x82 DATA 0x00 MASK 0xEF TPS65941111 Set AMUXOUT_EN and CLKMON_EN clear LPM_EN REG_WRITE_MASK_IMM ADDR 0x81 DATA 0x18 MASK 0xE3 Clear SPMI_LPM_EN REG_WRITE_MASK_IMM ADDR 0x82 DATA 0x00 MASK 0xEF Resource PMIC Delay Diagram Total Delay Rail Name nRSTOUT_SOC TPS65941213 Q1 0 us H_SOC_PORz_1V8 LDO3 TPS65941213 Q1 2500 us VDD_DLL...

Page 42: ...e does not result in a state change The event and sequence originate from the MCU_ONLY state and stays in the MCU_ONLY state In the sequence the recover counter found in register RECOV_CNT_REG_1 is incremented and the nRSTOUT MCU_PORz signal is driven low The MCU relevant BUCK and LDOs are reset to their default voltages at the time indicated in Figure 6 8 and finally the MCU_PORz signal is set hi...

Page 43: ...heir default values Since this sequence originates from the MCU_ONLY state these regulators are on 6 3 7 TO_MCU The TO_MCU sequence first turns off rails and GPIOs which are assigned to the SOC power group The sequence enables the MCU rails in the event that they are not already active when transitioning from STANDBY to MCU_ONLY for example There are two cases for this sequence based off the value...

Page 44: ...O9 TPS65941213 Q1 3500 us EN_MCU3V3IO_LDSW GPIO3 TPS65941111 Q1 4700 us EN_VDDR BUCK5 TPS65941111 Q1 500 us VDD_RAM_0V85 LDO3 TPS65941111 Q1 500 us VDD_IO_1V8 BUCK1234 TPS65941111 Q1 2500 us VDD_CORE_0V8 LDO4 TPS65941111 Q1 3000 us VDA_PLL_1V8 LDO1 TPS65941111 Q1 3500 us VDD_SD_DV LDO2 TPS65941111 Q1 3500 us VDD_USB_3V3 GPIO11 TPS65941111 Q1 3500 us EN_3V3IO_LDSW nRSTOUT TPS65941213 Q1 16200 us H_...

Page 45: ...00 us VDA_PLL_1V8 LDO1 TPS65941111 Q1 3500 us VDD_SD_DV LDO2 TPS65941111 Q1 3500 us VDD_USB_3V3 GPIO11 TPS65941111 Q1 3500 us EN_3V3IO_LDSW nRSTOUT TPS65941213 Q1 16200 us H_MCU_PORz_1V8 Figure 6 10 TO_MCU Sequence with I2C_7 low in both PMICs The last instructions of the TO_MCU sequence also perform writes to the MISC_CTRL and ENABLE_DRV_STAT registers after the delay defined in the PFSM_DELAY_RE...

Page 46: ...41213 Q1 1700 us VDD_PHY_1V8 LDO2 TPS65941213 Q1 3700 us VDD_MCUIO_1V8 LDO4 TPS65941213 Q1 1700 us VDA_MCU_1V8 LDO1 TPS65941213 Q1 1700 us VDD1_DDR_1V8 GPIO9 TPS65941213 Q1 0 us EN_MCU3V3IO_LDSW GPIO3 TPS65941111 Q1 3700 us EN_VDDR BUCK5 TPS65941111 Q1 3700 us VDD_RAM_0V85 LDO3 TPS65941111 Q1 3700 us VDD_IO_1V8 BUCK1234 TPS65941111 Q1 2700 us VDD_CORE_0V8 LDO4 TPS65941111 Q1 1700 us VDA_PLL_1V8 LD...

Page 47: ...igure 6 12 Note The I2C_7 bits need to be set or cleared by I2C in both PMICs before a trigger to the retention state occurs The I2C_7 trigger is not self clearing and must be maintained during operation In addition to the I2C_7 the processor must also configure the H_DDR_RET_1V1 signal on GPIO4 of the TPS65941111 device This signal is included in the Section 3 2 but is not part of the power seque...

Page 48: ...213 Q1 3500 us EN_MCU3V3IO_LDSW GPIO3 TPS65941111 Q1 500 us EN_VDDR BUCK5 TPS65941111 Q1 500 us VDD_RAM_0V85 LDO3 TPS65941111 Q1 500 us VDD_IO_1V8 BUCK1234 TPS65941111 Q1 2500 us VDD_CORE_0V8 LDO4 TPS65941111 Q1 3000 us VDA_PLL_1V8 LDO1 TPS65941111 Q1 3500 us VDD_SD_DV LDO2 TPS65941111 Q1 3500 us VDD_USB_3V3 GPIO11 TPS65941111 Q1 3500 us EN_3V3IO_LDSW EN_DRV TPS65941213 Q1 0 us EN_DRV Figure 6 12 ...

Page 49: ...500 us VDD_CORE_0V8 LDO4 TPS65941111 Q1 3000 us VDA_PLL_1V8 LDO1 TPS65941111 Q1 3500 us VDD_SD_DV LDO2 TPS65941111 Q1 3500 us VDD_USB_3V3 GPIO11 TPS65941111 Q1 3500 us EN_3V3IO_LDSW EN_DRV TPS65941213 Q1 0 us EN_DRV Figure 6 13 TO_RETENTION when I2C_7 is high in both PMICs At the end of the sequence both PMICs set the LPM_EN and clear the CLKMON_EN and AMUXOUT_EN The TPS65941213 device also perfor...

Page 50: ...tion 0 0 NA Retention 7 1 1 ACTIVE In this example the PMIC is already in the ACTIVE state after a normal power up event The PMIC is kept in the ACTIVE state by setting the NSLEEP1 and NSLEEP2 bits before clearing the ENABLE_INT Write 0x48 0x86 0x03 0xFC Set NSLEEP1 and NSLEEP2 in TPS65951213 Write 0x48 0x66 0x01 0xFE Clear BIST_PASS_INT Write 0x48 0x65 0x26 0xD9 Clear all potential sources of the...

Page 51: ...TANDBY state turns off all regulators which power the MCU Therefore it is required to select the state MCU ONLY or ACTIVE that the STANDBY state returns to When the ENABLE pin goes low the TO_STANDBY sequence is triggered When the ENABLE pin goes high again the destination state is dependent upon the STARTUP_DEST bits The TO_STANDBY sequence is also triggered by the I2C_0 trigger When triggered fr...

Page 52: ...sequence Unlike the GPIO the BUCK monitor can become part of the PFSM by assigning a group to the BUCK regulator and unmasking the OV UV interrupts Per the Table 5 7 the BUCK3_GRP_SEL and BUCK4_GRP_SEL are not assigned a group Table 7 3 Rail Group Associations Selected Rail group Selection PFSM Trigger Description No Group Assigned None OV UV can set nINT pin for MCU interrogation MCU Rail Group M...

Page 53: ...ed and must be re applied with every power cycle and transition through the hardware states www ti com Application Examples SLVUC99 JANUARY 2022 Submit Document Feedback Optimized Dual TPS6594 Q1 PMIC User Guide for Jacinto 7 DRA829 or TDA4VM Automotive PDN 0C 53 Copyright 2022 Texas Instruments Incorporated ...

Page 54: ... Reference Manual Rev B reference model Texas Instruments TPS6594 Q1 Power Management IC PMIC with 5 Bucks and 4 LDOs for Safety Relevant Automotive Applications data sheet Texas Instruments TPS6594 Q1 Safety Manual request through mySecure Texas Instruments TPS6594 Q1 Schematic PCB Checklist application note References www ti com 54 Optimized Dual TPS6594 Q1 PMIC User Guide for Jacinto 7 DRA829 o...

Page 55: ...o change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you will fully indemn...

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