for a complete description. The PMIC voltage domains indicated are for the PDN-0C NVM
configuration.
2. PMIC_Wake1 is typically a CAN PHY INH output.
3. WKUP2 triggers a transition to MCU Only state. LP_WKUP1 and WKUP1 transition to the ACTIVE state.
Note
The PMIC voltage domain of an IO can be different depending upon configuration. When configured
as an input GPIO3 and GPIO4 are in the VRTC domain. When configured as an output, GPIO3 and
GPIO4 are in the VINT domain.
Note
In addition to the I2C signals, four additional signals are open-drain outputs and require a pullup to a
specific power rail. Please refer to
for a list of the signals and the specific power rail.
Table 3-2. Open-drain signals and Power Rail
PDN Signal
Pullup Power Rail
H_MCU_INTn
VDD_MCUIO_3V3
H_MCU_PORz_1V8
VDA_MCU_1V8
H_SOC_PORz_1V8
VDA_MCU_1V8
H_DDR_RET_1V1
VDD_DDR_1V1_REG
H_WKUP_I2C0
VDD_MCUIO_3V3
H_MCU_I2C0_SCL/SDA
VDD_MCUIO_3V3
as a guide to understand GPIO assignments required for each PDN system feature. If the
feature listed is not required, the digital connection can be removed; however, the GPIO pin is still configured
per NVM defined default function shown. After the processor has booted up, the processor can reconfigure
unused GPIOs to support new functions. This is possible as long as that function is only needed after boot and
default function does not cause any conflicts with normal operations (for example, two outputs driving same net).
For details on how functional safety related connections help achieve functional safety system-level goals, see
Processor Connections
SLVUC99 – JANUARY 2022
Optimized Dual TPS6594-Q1 PMIC User Guide for Jacinto
™
7 DRA829 or
TDA4VM Automotive PDN-0C
9
Copyright © 2022 Texas Instruments Incorporated
