J721E EVM Hardware Architecture
79
SPRUIS4A – December 2019 – Revised May 2020
Copyright © 2019–2020, Texas Instruments Incorporated
Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
4.25.2.2
Optional Clock
Optionally, the reference clock can be supplied by the SERDES clock generator Mfr. Part Number#
CDCI6214RGET, located on Quad port Ethernet Expansion Board, which can be configured by I2C0 of
the J721E SOC. The I2C address of this clock generator is 0x77 and this address conflicts with CDCI
Chip on Common processor Board. An I2C switch on Quad port Ethernet Expansion Board is used to
remove the address conflict by either connecting any one of the clock generators.
Figure 59. CDCI I2C Isolation Circuit
Set the CDCI_I2C_SEL I/O EXP bit high to connect the I2C bus to the CDCI for programming on the
Quad Port Ethernet Expansion Board. During this time, the CDCI device U17 on the Common Processor
board should be in reset mode.
