Texas Instruments J721EXSOMXEVM, User Manual

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J721E EVM Hardware Architecture
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58 SPRUIS4A – December 2019 – Revised May 2020
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Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
Clock : A clock generator (CDCI #1) is provided to drive 100 MHz HCSL clock for PCIe add on cards and
J721e SoC. Resistor options are provided to select the clock source for host and end point operation.
For PCIe host operation:
• The add on cards can have clocks driven by SoC or clock generator. Selection can be made through
resistors as shown in
Table 31 .
Table 31. Reference Clock Selection for PCIe Host Operation
Clock Selected Mount Unmount
Reference Clock for SOC from clock
generator R214 R211, C44
R213 R210, C51
Reference Clock for PCIe connector from
SoC R211, C44 R214, R54
R210, C51 R213, R56
Reference Clock for PCIe connector from
clock generator R54 R211, C44
R56 R210, C51
For PCIe Endpoint operation:
• The SoC can have the clock driven by add on cards or clock generator. Selection can be made
through resistors as shown in
Table 32 .
Table 32. Reference Clock Selection for PCIe Endpoint Operation
Clock Selected Mount Unmount
Reference clock for SOC from clock
generator R214 R211, C44
R213 R210, C51
Reference clock for SOC from PCIe
connector R211, C44 R214, R54
R210, C51 R213, R56
Hot plug : The PRSNT1# and PRSNT2# signals are the hot plug presence detect signals. The PRSNT1#
is pulled up and PRSNT2# is connected to GPIO expander, so that PRSNT1# will be pulled low when a
add on card is plugged in as both the PRSNT signals in add on cards will be shorted. Optional resistor is
provided to short the PRSNT1# and PRSNT2# to support host and device mode.
For choosing Host or device operation of PCIe card, the following resistors must be mounted/unmounted
as mentioned in
Table 33 .
Table 33. Resistors for Selecting PCIe Card Host or Device Operation
Mode Mount Demount
Host mode R631 R630
R638
Device mode R630 R631
R638