Texas Instruments ISO5852SDWEVM-017, User Manual, Page: 6 / 37

Inv Rec
+15 V
Vdrp1
S2
Vdrn1
DC-DC
V
CC
Rx Tx
GND1 V
EE2
RST
RDY
FLT
IN+
IN
±
V
CC1
V
CC2
DESAT
GND2
OUTH
OUTL
CLAMP
V
CC1
V
CC1
UVLO1
Mute
Decoder
Q S
R Q
V
CC1
V
CC1
Gate Drive
and
Encoder
Logic
UVLO2
2 V
9 V
500 µA
STO
V
CC2
Ready
Fault
GND1 V
EE2
RST
RDY
FLT
IN+
IN ±
V
CC1
V
CC2
DESAT
GND2
OUTH
OUTL
CLAMP
V
CC1
V
CC1
UVLO1
Mute
Decoder
Q S
R Q
V
CC1
V
CC1
Gate Drive
and
Encoder
Logic
UVLO2
2 V
9 V
500 µA
STO
V
CC2
Ready
Fault
10
10
Vdrp2
Vdrn1
V
CC
Logic Block
Inv Rec
+15 V
Vdrp1
S1
Vdrn1
DC-DC
V
CC
Rx Tx
Reinforced Isolation
10
10
S1
S2
V
CC
5 V
AMC1301
Vdrn2
V
CC
±
5 V
Vdrp1
BUS_P
BUS_N
VCC_5V
GND
INU+
FU
RST
INL+
FL
F
TRO_P
TRO_N
DU
SU
GU
DL
SL
GL
TR_N
DU
TR_P
±
5 V
Overview
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6 SLLU298 – May 2018
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ISO5852SDW Driving and Protecting SiC and IGBT Power Modules
1.3.2 Block Diagram
The ISO5852SDWEVM-017 board block diagram is shown in Figure 1 .
Figure 1. ISO5852SDWEVM-017 EVM Block Diagram