Texas Instruments DS125RT410 Manual Download Page 4

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DS125RT410

SNLS459 – APRIL 2011

www.ti.com

Pin Descriptions

Pin Name

Pin #

I/O, Type

Description

HIGH-SPEED DIFFERENTIAL I/O

RXP0

I, CML

Inverting and non-inverting CML-compatible differential inputs to the equalizer.

RXN0

Nominal differential input impedance = 100

Ω

RXP1

I, CML

Inverting and non-inverting CML-compatible differential inputs to the equalizer.

RXN1

Nominal differential input impedance = 100

Ω

RXP2

I, CML

Inverting and non-inverting CML-compatible differential inputs to the equalizer.

RXN2

Nominal differential input impedance = 100

Ω

RXP3

I, CML

Inverting and non-inverting CML-compatible differential inputs to the equalizer.

RXN3

Nominal differential input impedance = 100

Ω

TXP0

O, CML

Inverting and non-inverting CML-compatible differential outputs from the driver.

TXN0

Nominal differential output impedance = 100

Ω

TXP1

O, CML

Inverting and non-inverting CML-compatible differential outputs from the driver.

TXN1

Nominal differential output impedance = 100

Ω

TXP2

O, CML

Inverting and non-inverting CML-compatible differential outputs from the driver.

TXN2

Nominal differential output impedance = 100

Ω

TXP3

O, CML

Inverting and non-inverting CML-compatible differential outputs from the driver.

TXN3

Nominal differential output impedance = 100

Ω

LOOP FILTER CONNECTION PINS

LPF_CP_0

I/O, analog

Loop filter connection

LPF_REF_0

Place a 22 nF ± 10% Capacitor between LPF_CP_0 and LPF_REF_0

LPF_CP_1

I/O, analog

Loop filter connection

LPF_REF_1

Place a 22 nF ± 10% Capacitor between LPF_CP_1 and LPF_REF_1

LPF_CP_2

I/O, analog

Loop filter connection

LPF_REF_2

Place a 22 nF ± 10% Capacitor between LPF_CP_2 and LPF_REF_2

LPF_CP_3

I/O, analog

Loop filter connection

LPF_REF_3

Place a 22 nF ± 10% Capacitor between LPF_CP_3 and LPF_REF_3

REFERENCE CLOCK I/O

REFCLK_IN

I, 2.5V analog

Input is 2.5 V, 25 MHz ± 100 ppm reference clock from external oscillator
No stringent phase noise requirement

REFCLK_OUT

O, 2.5V analog

Output is 2.5 V, buffered replica of reference clock input for connecting multiple
DS125RT410s on a board.

LOCK INDICATOR PINS

LOCK0

O, 2.5V

Output is 2.5 V, the pin is high when CDR lock is attained on the corresponding

LOCK1

LVCMOS

channel.

LOCK2

Note that these pins are shared with SMBus address strap input functions read

LOCK3

at startup.

SMBus MASTER MODE PINS

ALL_DONE

O, 2.5V

Output is 2.5 V, the pin goes low to indicate that the SMBus master

LVCMOS

EEPROMread has been completed.

READ_EN

I, 2.5V

Input is 2.5 V, a transition from high to low starts the load from the external

LVCMOS

EEPROM. The READ_EN pin must be tied low when in SMBus slave mode.

INTERRUPT OUTPUT

INT

O, 3.3V

Used to signal horizontal or vertical eye opening out of tolerance, loss of signal

LVCMOS, Open detect, or CDR unlock.

Drain

External 2K

to 5K

pull-up resistor is required.

Pin is 3.3 V LVCMOS tolerant.

SERIAL MANAGEMENT BUS (SMBus) INTERFACE

EN_SMB

I, 2.5V analog

Input is 2.5 V, selects SMBus master mode or SMBus slave mode.
EN_SMB = High for slave mode
EN_SMB = Float for master mode
Tie READ_EN pin low for SMBus slave mode. See

Table 3

SDA

I/O, 3.3V

Data Input / Open Drain Output

LVCMOS, Open External 2K

to 5K

pull-up resistor is required.

Drain

Pin is 3.3 V LVCMOS tolerant.

SDC

I/O, 3.3V

Clock Input / Open Drain Clock Output

LVCMOS, Open External 2K

to 5K

pull-up resistor is required.

Drain

Pin is 3.3 V LVCMOS tolerant.

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DS125RT410

Summary of Contents for DS125RT410

Page 1: ...rate Operating temperature range of 40 to 85 C from 9 8 to 12 5 Gbps and associated sub rates div RHS 48 pin 7 mm x 7 mm package by 2 4 and 8 to support a variety communication protocols A 25 MHz reference clock is required Easy pin compatible upgrade between which need not be synchronous with the serial data repeater and retimers DS100RT410 EQ CDR DE 10 3125 Gbps The programmable settings can be ...

Page 2: ...hers SFP SFF8431 QSFP DS125RT410 SNLS459 APRIL 2011 www ti com These devices have limited built in ESD protection The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates Typical Application Diagram 2 Submit Documentation Feedback Copyright 2011 Texas Instruments Incorporated Product Folder Links DS125R...

Page 3: ...1 RXP0 36 TXP0 32 TXN1 DS125RT410 DAP GND LP F_CP_ 3 LP F_REF_3 VDD LOCK_3 ADDR_3 SDC SDA REFCLK_IN EN_SMB LOCK_2 ADDR_2 GND LP F_REF_2 LP F_CP_ 2 7 mm x 7 mm 0 5 mm pitch LP F_REF_1 LP F_CP_ 1 GND LOCK_1 ADDR_1 ALL_DONE REFCLK_OUT INT READ_EN LOCK_0 ADDR_0 VDD LP F_REF_0 LP F_CP_ 0 4 DS125RT410 www ti com SNLS459 APRIL 2011 Connection Diagram Copyright 2011 Texas Instruments Incorporated Submit D...

Page 4: ...d LPF_REF_2 LPF_CP_3 14 I O analog Loop filter connection LPF_REF_3 13 Place a 22 nF 10 Capacitor between LPF_CP_3 and LPF_REF_3 REFERENCE CLOCK I O REFCLK_IN 19 I 2 5V analog Input is 2 5 V 25 MHz 100 ppm reference clock from external oscillator No stringent phase noise requirement REFCLK_OUT 42 O 2 5V analog Output is 2 5 V buffered replica of reference clock input for connecting multiple DS125R...

Page 5: ...XPn RXNn 0 5V to 2 75V Signal Output Voltage TXPn TXNn 0 5V to 2 75V Junction Temperature 150 C Storage Temperature 65 C to 150 C ESD Rating HBM STD JESD22 A114F 6 kV MM STD JESD22 A115 A 250 V CDM STD JESD22 C101 D 1250 V Thermal Resistance θJA No Airflow 4 layer JEDEC 9 thermal vias 26 1 C W For soldering specifications see product folder at http www ti com lit an snoa549c snoa549c pdf 1 Absolut...

Page 6: ...V VIL Low Level Input Voltage VDD 2 5 V GND 0 7 V VOL Low Level Output Voltage IPULLUP 3mA 0 4 V IIH Input High Current VIN 3 6 V VDD 2 5V 20 40 μA IIL Input Low Current VIN GND VDD 2 5V 10 10 μA fSDC SMBus clock rate 100 400 KHz DATA BIT RATES RB Bit Rate Range 9 8 12 5 Gbps SIGNAL DETECT SDH Signal Detect ON Threshold Level Default input signal level to assert 70 mVp p signal detect 10 3125 Gbps...

Page 7: ...gister control to 15 dB maximum de emphasis setting Relative to the nominal 0 dB de emphasis level set at the minimum de emphasis setting tR tF Transition time rise and fall Transition time control Full Slew 39 ps times 8 9 Rate Transition time control Limited 50 ps Slew Rate LRO Maximum Differential Output 100 MHz 6 GHz 10 15 dB Return Loss SDD22 tDP Propagation Delay Retimed data 300 ps TDE De e...

Page 8: ...between TXPn and TXNn for any 3 ps output CLOCK AND DATA RECOVERY BWPLL PLL Bandwidth Measured at 10 3125 Gbps 5 MHz 3 dB JTOL Input sinusoidal jitter tolerance Measured at BER 10 15 10 kHz to 250 MHz sinusoidal jitter 0 6 UI frequency JTRANS Jitter Transfer Measured at BER 10 15 Sinusoidal jitter at 10 MHz jitter 6 dB frequency TLOCK CDR Lock Time Measured at 10 3125 Gbps 15 ms 8 Submit Documenta...

Page 9: ...0 Data Path Block Diagram One of Four Channels Device Data Path Operation The data path operation of the DS125RT410 comprises three functional sections as shown in the data path block diagram of Figure 1 The three functional sections are as follows Channel Equalization Clock and Data Recovery Output Driver Channel Equalization Physical transmission media such as traces on printed circuit boards PC...

Page 10: ...hrough the available VCO coarse tuning settings and counts the divided VCO frequency using the 25 MHz reference as a clock source The VCO coarse tuning setting which provides the VCO frequency closest to the required frequency is stored and this coarse tuning setting is used for subsequent operation This produces a fast robust phase lock to the input signal Output Driver The DS125RT410 is commonly...

Page 11: ...tect incorrect lock conditions which can arise when the input data signals are strongly periodic This condition is referred to as false lock The DS125RT410 discriminates against false lock by using its 25 MHz reference to ensure that the VCO frequency resulting from its internal phase locking process is correct To determine the correct VCO frequency the digital circuitry in the DS125RT410 requires...

Page 12: ...gister 0x60 will contain 0x00 Register 0x61 will contain 0xb2 For the example we are considering Group 1 is for 10 GbE Here the actual data rate for the 64 66B encoded 10 GbE data is 10 3125 Gbps For 10 GbE the retimer automatically uses a divide ratio of 1 so the VCO frequency is also 10 3125 GHz For 10 GbE we compute the expected PPM count as NPPM 10 3125 X 1280 13 200 Again this is a decimal va...

Page 13: ...desired The register configuration procedure is as follow 1 Select the desired channel of the DS125RT410 by writing the appropriate value to register 0xff 2 Set bits 5 4 of register 0x36 to a value of 2 b11 as described above to enable the 25 MHz reference clock 3 Write registers 0x2f with the correct values 4 Compute the expected PPM count values for Group 0 and Group 1 as described above 5 Write...

Page 14: ...K_IN pin 19 is for reference clock input A 25 MHz oscillator should be connected to pin 19 See Electrical Characteristics for the requirements on the 25 MHz clock The frequency of the reference clock should always be 25 MHz no matter what data rate or mode of operation is used Reference Clock Out REFCLK_OUT pin 42 is the reference clock output pin The DS125RT410 drives a buffered replica of the 25...

Page 15: ...can be set using the SMBus control for each channel If any interrupt occurs registers in the DS125RT410 latch in information about the event that caused the interrupt This can then be read out by the controller over the SMBus LOCK_3 LOCK_2 LOCK_1 and LOCK_0 Each channel of the DS125RT410 has an independent lock indication pin These lock indication pins LOCK_3 LOCK_2 LOCK_1 and LOCK_0 are pin 16 pi...

Page 16: ...om the external EEPROM when the READ_EN pin goes low When the DS125RT410 is finished reading its configuration from the external EEPROM it drives its ALL_DONE pin low After the DS100RT410 has finished reading its configuration from the EEPROM it releases control of the SMBus and becomes a SMBus slave In applications where there is more than one DS125RT410 on the same SMBus bus contention can resul...

Page 17: ...de the SMBus address is latched in on the address strap lines on power up In SMBus slave mode if the READ_EN pin is not tied low the DS125RT410 will not latch in the address on its address strap lines It will instead latch in an SMBus write address of 0x30 regardless of the state of the address strap lines This is a test feature Obviously a system with multiple retimers cannot operate properly if ...

Page 18: ...in SMBus slave mode i e when the EN_SMB pin pin 20 is tied high the DS125RT410 will revert to an SMBus write address of 0x30 This is a test feature If there are multiple DS125RT410s on the same SMBus they will all revert to an SMBus write address of 0x30 which can cause SMBus collisions and failure to access the DS125RT410s over the SMBus Table 4 DS125RT410 SMBus Write Address Assignment ADDR_3 AD...

Page 19: ...ting to and Reading from the Control Shared Registers Any write operation targeting register 0xff writes to the control shared register 0xff This is the only register in the DS125RT410 with an address of 0xff Bit 2 of register 0xff is used to select either the control shared register set or a channel register set If bit 2 of register 0xff is cleared written with a 0 then all subsequent read and wr...

Page 20: ...gister 0x00 bits 7 4 and register 0x06 bits 3 0 In order to communicate with the DS125RT410 over the SMBus it is necessary for the SMBus controller to know the address of the DS125RT410 The address strap observation bits in control shared register 0x00 are primarily useful as a test of SMBus operation There is no way to get the DS125RT410 to tell you what its SMBus address is unless you already kn...

Page 21: ...its external EEPROM when triggered by register 0x04 bit 4 as described below When register 0x04 bit 4 is set the DS125RT410 reads its configuration from an external EEPROM over the SMBus immediately When this bit is set the DS125RT410 does not wait until the READ_EN pin is pulled low to read from the EEPROM This EEPROM read occurs whether the DS125RT410 is in SMBus master mode or not If the read f...

Page 22: ...register is written Always write 0x0 to the four MSBs of register 0xff The register set target selected by each valid value written to the channel select register is shown in Table 6 Table 6 Channel Select Register Values Mapped to Register Set Target Register 0xff Value hex Shared Channel Broadcast Channel Targeted Channel Comments Register Selection Register Selection Selection 0x00 Shared N A N...

Page 23: ..._divsel_ov Enable Override Divider Select Register 0x18 0x0a 3 0x0 R W reg_cdr_reset_ov Enable CDR Reset Override Register 0x0a 2 0x0 R W reg_cdr_reset_sm CDR Reset Override Bit 0x0b 4 0 0x0f R W cdr_cap_dac_start1 4 Override VCO Cap 0 DAC Setting 1 4 0 0x0d 5 0x0 R W PRBS_PATT_SHIFT_ PRBS Generator EN Clock Enable 0x11 7 6 0x0 R W eom_sel_vrange 1 0 Eye Opening Monitor Voltage Range 1 0 5 0x1 R W...

Page 24: ...ng Monitor Timer Threshold 7 0 0x2d 2 0 0x0 R W drv_sel_vod 2 0 Driver VOD 2 0 0x2f 7 6 0x0 R W RATE 1 0 Rate 1 0 5 4 0x0 R W SUBRATE 1 0 Subrate 1 0 3 0x0 R W index_ov CTLE Adaptation Index Override Register 0x13 2 0x1 R W en_ppm_check Enable Frequency Counter for Lock Detect 1 0x1 R W en_fld_check False Lock Detector for lock detect is disabled by default Must set bit to 0 to enable the FLD 0 0x...

Page 25: ...LE Stage 1 Boost Setting for Lower Data Rates 1 0 3 2 0x1 R W fixed_eq_BST2 1 0 Fixed CTLE Stage 2 Boost Setting for Lower Data Rates 1 0 1 0 0x1 R W fixed_eq_BST3 1 0 Fixed CTLE Stage 3 Boost Setting for Lower Data Rates 1 0 0x3e 7 0x1 R W HEO_VEO_LOCKMO Enable HEO VEO N_EN Lock Monitoring 0x40 0x5f CTLE Settings for Adaptation see Table 14 0x6a 7 4 0x4 R W veo_lck_thrsh 3 0 Vertical Eye Opening ...

Page 26: ...as occurred because the CDR has fallen out of lock or because the signal is no longer detected at the input then bit 4 and or bit 0 of register 0x01 will go high indicating the cause of the interrupt In either case the control shared register set will indicate which channel caused the interrupt This is read from bits 3 0 of control shared register 0x05 When an interrupt is detected by the controll...

Page 27: ...verridden but the DS125RT410 may still lose lock If this happens the DS125RT410 will attempt to reacquire lock if the reference mode is set appropriately and if the rate subrate code is set to permit it the DS125RT410 will begin searching for CDR lock at the highest allowable VCO divider ratio that is at the lowest configured bit rate At this lowest bit rate the CTLE boost settings used will come ...

Page 28: ...ocked 0x6 N A Invalid Setting 0x5 10 MHz Clock Internal 10 MHz clock Clock frequency may not be precise 0x4 PRBS Generator PRBS Generator must be enabled to output PRBS sequence 0x3 VCO Q Clock Register 0x09 bit 4 and register 0x1e bit 0 must be set to enable the VCO Q Clock 0x2 VCO I Clock 0x1 Retimed Data Default when the retimer is locked 0x0 Raw Data If the output multiplexer is not overridden...

Page 29: ... the PRBS generator if it is enabled will be synchronous to the input signal When a signal is present at the input it might be desired to output the raw data in order to see the effects of the CTLE without the CDR It might also be desired to enable the PRBS generator and output this signal replacing the data content of the input signal with the internally generated PRBS sequence Overriding the VCO...

Page 30: ... Next write a 1 to bit 2 of register 0x09 This enables the VCO divider override Then set the VCO divider ratio by writing to register 0x18 as shown in Table 10 For an output frequency of approximately 10 3125 GHz set the divider ratio to 1 by writing 0x0 to bits 6 4 of register 0x18 Do not clear bit 3 when you write a 1 to bit 2 of register 0x09 Now write a 1 to bit 7 of register 0x09 This enables...

Page 31: ...easurement makes it useful for determining the adaptation figure of merit In normal operation the HEO and VEO are automatically measured periodically to determine whether the DS125RT410 is still in lock Reading registers 0x27 and 0x28 will yield the most recently measured HEO and VEO values In normal operation the eye monitor circuitry is powered down most of the time to save power When the eye is...

Page 32: ...oltage range from 100 mV to 400 mV The EOM voltage range is normally set by the CDR state machine during lock and adaptation but the range can be overridden by writing a two bit code to bits 7 6 of register 0x11 The values of this code and the corresponding EOM voltage ranges are shown in Table 11 Table 11 EOM Voltage Range vs Bits 7 6 of Register 0x11 Value in Bits 7 6 of Register 0x11 EOM Voltag...

Page 33: ...is cleared by default Inverting the Output Polarity Register 0x1f bit 7 In some systems the polarity of the data does not matter In systems where it does matter it is sometimes necessary for the purposes of trace routing for example to invert the normal polarities of the data signals The DS125RT410 can invert the polarity of the data signals by means of a register write Writing a 1 to bit 7 of reg...

Page 34: ...mode is used if the transmission channel response is fixed Mode 1 Only the CTLE is adapted to equalize the transmission channel This mode is primarily used for smoothly varying high loss transmission channels such as cables and simple PCB traces Bits 6 5 of register 0x31 determine the adaptation mode to be used The mapping of these register bits to the adaptation algorithm is shown in Table 13 Tab...

Page 35: ...ns Overriding the CTLE Settings Used for CTLE Adaptation Register 0x2c bits 3 0 Register 0x2f bit 3 Register 0x39 bits 4 0 and Registers 0x50 0x5f The CTLE adaptation algorithm operates by setting the CTLE boost stage controls to a set of pre determined boost settings each of which provides progressively more high frequency boost At each stage in the adaptation process the DS125RT410 attempts to p...

Page 36: ...tive to or in conjunction with writing the CTLE boost setting registers 0x40 through 0x5f it is possible to set the starting CTLE boost setting index To override the default setting which is 0 set bit 3 of register 0x2f When this bit is set the starting index for adaptation comes from register 0x39 bits 4 0 This is the index into the CTLE settings table in registers 0x40 through 0x5f When this sta...

Page 37: ...h make up the bit field dvr_dem 2 0 and register 0x15 bit 6 which is the third de emphasis setting bit The available driver de emphasis settings and the mapping to these bits are shown in Table 16 Table 16 Driver De Emphasis Settings Register 0x15 Bit 2 Register 0x15 Bit 1 Register 15 Bit 0 Register 0x15 Bit 6 De emphasis Setting dvr_dem 2 drv_dem 1 drv_dem 0 drv_dem_range dB 0 0 0 X 0 0 0 0 1 1 1...

Page 38: ...ree RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retar...

Page 39: ...PQ Reel Diameter mm Reel Width W1 mm A0 mm B0 mm K0 mm P1 mm W mm Pin1 Quadrant DS125RT410SQ NOPB WQFN RHS 48 1000 330 0 16 4 7 3 7 3 1 3 12 0 16 0 Q1 DS125RT410SQE NOPB WQFN RHS 48 250 178 0 16 4 7 3 7 3 1 3 12 0 16 0 Q1 PACKAGE MATERIALS INFORMATION www ti com 24 Apr 2013 Pack Materials Page 1 ...

Page 40: ...age Type Package Drawing Pins SPQ Length mm Width mm Height mm DS125RT410SQ NOPB WQFN RHS 48 1000 367 0 367 0 38 0 DS125RT410SQE NOPB WQFN RHS 48 250 213 0 191 0 55 0 PACKAGE MATERIALS INFORMATION www ti com 24 Apr 2013 Pack Materials Page 2 ...

Page 41: ...MECHANICAL DATA RHS0048A www ti com SQA48A Rev B ...

Page 42: ...esponsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failur...

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