SNLS459 – APRIL 2011
Table 7. Channel Registers (continued)
Address (Hex)
Bits
Default Value (Hex)
Mode
Field Name
Description
0x33
7:4
0x8
R/W
heo_thresh[3:0]
HEO Threshold for
CTLE Adaptation
Handoff
3:0
0x8
R/W
veo_thresh[3:0]
VEO Threshold for
CTLE Adaptation
Handoff
0x36
6
0x0
R/W
heo_veo_int_enable
Enable HEO/VEO
Interrupt
5:4
0x3
R/W
ref_mode[1:0]
Reference Clock
Mode <1:0>
2
0x0
R/W
mr_cdr_cap_dac_rng
Enable Override for
_ov
VCO Cap DAC
Range
1:0
0x1
R/W
mr_cdr_cap_dac_rng[ Cap DAC Range
1:0]
<1:0>
0x39
4:0
0x0
R/W
start_index[4:0]
Start Index for CTLE
Adaptation <4:0>
(Enable from Register
0x2f, Bit 3)
0x3a
7:6
0x2
R/W
fixed_eq_BST0[1:0]
Fixed CTLE Stage 0
Boost Setting for
Lower Data Rates
<1:0>
5:4
0x2
R/W
fixed_eq_BST1[1:0]
Fixed CTLE Stage 1
Boost Setting for
Lower Data Rates
<1:0>
3:2
0x1
R/W
fixed_eq_BST2[1:0]
Fixed CTLE Stage 2
Boost Setting for
Lower Data Rates
<1:0>
1:0
0x1
R/W
fixed_eq_BST3[1:0]
Fixed CTLE Stage 3
Boost Setting for
Lower Data Rates
<1:0>
0x3e
7
0x1
R/W
HEO_VEO_LOCKMO Enable HEO/VEO
N_EN
Lock Monitoring
0x40 – 0x5f
CTLE Settings for Adaptation – see
0x6a
7:4
0x4
R/W
veo_lck_thrsh[3:0]
Vertical Eye Opening
Lock Threshold <3:0>
3:0
0x4
R/W
heo_lck_thrsh[3:0]
Horizontal Eye
Opening Lock
Threshold <3:0>
0x6b
7:0
0x0
R/W
fom_a[7:0]
Adaptation Figure of
Merit Term a<7:0>
0x6c
7:0
0x0
R/W
fom_b[7:0]
Adaptation Figure of
Merit Term b<7:0>
0x6d
7:0
0x0
R/W
fom_c[7:0]
Adaptation Figure of
Merit Term c<7:0>
0x6e
7
0x0
R/W
en_new_fom_ctle
Enable Alternate
Figure of Merit for
CTLE Adaptation
0x70
2:0
0x3
R/W
eq_lb_cnt[2:0]
CTLE Adaptation
Look-Beyond Count
<2:0>
Copyright © 2011, Texas Instruments Incorporated
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