SNLS459 – APRIL 2011
The second step is to override the output multiplexer setting. This is accomplished by setting bit 5 of register
0x09, the output multiplexer override. Once this bit is set, the value of register 0x1e, bits 7:5 will control the
output of the channel. Note that if either retimed or raw data is selected, the output will just be noise. The device
output may saturate to a static 1 or 0.
If there is no signal, the VCO clock will be free-running. Its frequency will depend upon the divider and CAP DAC
settings and it will vary from part to part and over temperature.
If the PRBS generator is enabled, the PRBS generator output can be selected. This can either be at a data rate
determined by the free-running VCO or at a data rate determined by the input signal, if one is present. If a signal
is present at the input and the DS125RT410 can lock to it, the output of the PRBS generator will be synchronous
with the input signal, but the bit stream output will be determined by the PRBS generator selection.
The 10 MHz clock is always available at the output when the output multiplexer is overridden. The 10 MHz clock
is a free-running oscillator in the DS125RT410 and is not synchronous to the input or to anything else in the
system. The clock frequency will be approximately 10 MHz, but this will vary from part to part.
If there is a signal present at the input, it is not necessary to override the signal detect. Clearing bits 7 and 6 of
register 0x14 will return control of the signal detect to the DS125RT410. Normally, when the retimer is locked to
a signal at its input, it will output retimed data. However, if desired, the output multiplexer can be overridden in
this condition to output raw data. It can also be set to output any of the other signals shown in
. If there is
an input signal, and if the DS125RT410 is locked to it, the VCO I-Clock, the VCO Q-Clock, and the output of the
PRBS generator, if it is enabled, will be synchronous to the input signal.
When a signal is present at the input, it might be desired to output the raw data in order to see the effects of the
CTLE without the CDR. It might also be desired to enable the PRBS generator and output this signal, replacing
the data content of the input signal with the internally-generated PRBS sequence.
Overriding the VCO Divider Selection
Register 0x09, bit 2, and Register 0x18, bits 6:4
In normal operation, the DS125RT410 sets its VCO divider to the correct divide ratio, either 1, 2, 4, 8, or 16,
depending upon the bit rate of the signal at the channel input. It is possible to override the divider selection. This
might be desired if the VCO is set to free-run, for example, to output a signal at a sub-harmonic of the actual
VCO frequency.
In order to override the VCO divider settings, first set bit 2 of register 0x09. This is the VCO divider override
enable. Once this bit is set, the VCO divider setting is controlled by the value in register 0x18, bits 6:4. The valid
values for this three-bit field are 0x0 to 0x4. The mapping of the bit field values to the divider ratio is shown in
Table 10. Divider Ratio Mapping to Register 0x18, Bits 6:4
Bit Field Value
Divider Ratio
0
1
1
2
2
4
3
8
4
16
In normal operation, the DS125RT410 will determine the required VCO divider ratio automatically. The most
common application for overriding the divider ratio is when the VCO is set to free-run. Normally the divider ratio
should not be overridden except in this case.
Using the PRBS Generator
Register 0x0d, bit 5, Register 0x1e, bit 4, and Register 0x30, bit 3 and bits 1:0
The DS125RT410 includes an internal PRBS generator which can generate standard PRBS-9 and PRBS-31 bit
sequences. The PRBS generator can produce a PRBS sequence that is synchronous to the incoming data
signal, or it can generate a PRBS sequence using the internal free-running VCO as a clock. Both modes of
operation are described in the paragraphs that follow.
Copyright © 2011, Texas Instruments Incorporated
29
Product Folder Links:
