Dual DP83640 Ethernet PHY HSMC Daughter Board
Reference Guide
V1.0 - October 2013
17
7.2 Pin out description
The following table describes the pin functions. The suffix _0/_1 corresponds to the PHY1/2
respectively.
Table 6: HSMC Connector Pin out Description
Function/Name
Direction
(at PHY)
Description
reset_n
input
Hardware reset when driven low (0). Must be 1 during
normal operation.
Use of the dedicated reset is not required as the power-on
reset should be sufficient. Can be used as necessary.
ref_clk_x1
input
A 25MHz clock source. It is connected to the X1 input of
PHY1 providing the reference clock source for the devices.
MDIO Management
mdc
in
Management clock input. The device supports up to 25MHz
(standard is 2.5 MHz).
Note: only one MDIO interface is available and all PHY
devices communicate through this single interface using
different MDIO addresses.
mdio
inout
Management data input/output
A 1.5K resistor to VCC is wired to it on the daughter board.
RMII Parallel MAC Interface PHY 1
rxclk_0
out
50 MHz RMII reference clock from PHY 1
rxcol_0
out
Receive collision indication from PHY. Used in half-duplex
only.
rxcrs_0 (crs_dv)
out
Receive carrier sense/data valid indication from PHY.
rxd[1:0]_0
out
RMII receive data.
rxdv_0
out
receive data valid from PHY 1
rxer_0
out
receive error indication from PHY 1
txd[1:0]_0
in
Transmit data to PHY 1.
txen_0
in
transmit enable to PHY 1
RMII Parallel MAC Interface PHY 2
rxcol_0
out
Receive collision indication from PHY 2. Used in half-duplex
only.
