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Dual DP83640 Ethernet PHY HSMC Daughter Board

Reference Guide

V1.0 - October 2013

5 Power-Up Strap Options

When the board powers up it is configured to the following settings. Each PHY has slightly
different settings as they have different modes of operation.

PHY 1 is configured in RMII Master Mode.

PHY 2 is configured in RMII Slave Mode.

5.1 PHY 1 Strap Options



PHY Address set to 1



Mode set to RMII

Master



Auto negotiation is enabled for all ports



Automatic cable crossover is enabled for all ports



The optional clk_out clock output of the PHY is enabled

Refer to the DP83640 datasheet for full detail.

The "wiring" column indicates what kind of strap-option is used on the pin:



A wiring of 'pull-up' means a pull-up (2.2K to VCC) is wired.



A wiring of 'pull-down' means a pull-down (2.2K to GND) is wired.



A wiring of "nc" means that pin has no strapping resistor connected to it.

Table 2: PHY 1 Power-Up Strap Options

Strap
Function

Pin

Pin#

Wiring

Value

Setting/Note

PHYAD0

COL

PHYADDR=1
(=default)

PHYAD1

RXD_3

PHYAD2..4

RXD_2.._0

44..46 nc

000

AN_EN

LED_LINK

Autoneg enable
Note: LED must be
wired to VCC

AN1

LED_SPEED

all modes

AN0

LED_ACT

CLK_OUT_EN GPIO1

pull-up

enable clock output

FX_EN_Z

RX_ER

disable FX mode

LED_CFG

CRS

mode1

MII_MODE

RX_DV

pull-up

RMII Mode

PCF_EN

GPIO2

RMII_MAS

TXD_3

pull-up

enable RMII master
mode

Summary of Contents for DP83640

Page 1: ...Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1 0 October 2013 1 HSMC Ethernet 2 Port 1588 Precision Timing PHY Daughter Board Reference Guide ...

Page 2: ...plication HSMC General Purpose I O J4 9 4 CLOCK DISTRIBUTION MAC INTERFACE CLOCKING 10 5 POWER UP STRAP OPTIONS 11 5 1 PHY 1 STRAP OPTIONS 11 5 2 PHY 2 STRAP OPTIONS 12 6 MDIO MANAGEMENT 13 7 HIGH SPEED MEZZANINE CARD HSMC CONNECTOR 14 7 1 HSMC CONNECTOR PIN OUT TABLE 14 7 2 PIN OUT DESCRIPTION 17 8 PLCC 44 SOCKET 19 9 PIN OUT FOR ALTERA STRATIX II GX PCIE BOARD 21 10 PIN OUT FOR ALTERA CYCLONE II...

Page 3: ...nnector Pin out Description 17 Table 7 PLCC 44 Socket Pin Description 20 Table 8 HSMC Interface Signals Stratix II GX PCIe Board 21 Table 9 HSMC Interface Signals Cyclone III Starter Kit Board 23 List of Figures Figure 1 Daughter Board 4 Figure 2 Board Block Diagram 6 Figure 3 Board Components 7 Figure 4 GPIO Connector J2 J3 8 Figure 5 Application General Purpose I O Connector J4 9 Figure 6 Clock ...

Page 4: ...nector to the main board that implements parallel RMII and provides the necessary 3 3V power supply In combination with the MorethanIP Nine Ways Ethernet Cores e g MAC Switch IEEE 1588 the PHY daughter board can be used to quickly design implement prototype and test embedded Ethernet Telecom or Industrial applications with support for precise timing according to the IEEE 1588 standard The board is...

Page 5: ...HY Management Interface MDIO MDC for configuration status 2x Standard Ethernet Copper RJ45 connector 10 100 Base T Status LEDs for current speed link and traffic indications 4 General Purpose I Os for timing event generation and capture 5 General Purpose I Os available to the application 168pin High Speed Mezzanine Card HSMC Connector to main board providing power supply and I O interfaces Single ...

Page 6: ...ed magnetics The MAC interfaces are available at the HSMC connector using 2 5V 3 3V LVTTL LVCMOS signaling 1 HSMC Connector National PHY1 DP83640 National PHY2 DP83640 RJ45 integrated Transformer General Purpose Connector 5x2 Connector 4x2 RMII Connector 4x2 Testsignals Testsignals PLCC 44 Socket Optional OTP Device 50MHz RJ45 integrated Transformer 25MHz Refclk 3 3V Power Figure 2 Board Block Dia...

Page 7: ...Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1 0 October 2013 7 3 2 Board Components Port0 Port1 genio Figure 3 Board Components ...

Page 8: ...D It is possible to configure the PHY to operate the LEDs in Mode 2 by writing into MDIO register 0x19 clearing bits 5 6 In this mode the link led will be on when the link is established and then blink on activity 3 2 2 PHY Generic I O GPIO J2 J3 Each PHY provides several general purpose I O pins for event generation and event capture Four of these gpio1 4 are available on a 5x2 connector on the d...

Page 9: ...chronization of the internal 1588 timers during operation 3 2 3 Application HSMC General Purpose I O J4 For arbitrary purposes a 5x2 connector J4 provides 5 signals that can be used for any implementation specific function The signals are available at the HSMC connector only 2 4 6 8 10 1 3 5 7 9 5x2 GND genio0 GND GND GND genio1 genio2 genio3 to HSMC GND genio4 Figure 5 Application General Purpose...

Page 10: ...I interface clock on its rx_clk and tx_clk outputs The PHYs are configured see Strap Options see section 5 2 to provide the internal synchronized IEEE 1588 clock on its clk_out pin which is available to the HSMC for use by 1588 related functions of the application 3 National PHY 1 DP83640 RMII Master National PHY 2 DP83640 RMII Slave RMII 50MHz X1 X1 50MHz rx_clk tx_clk 50MHz Reference to MAC clk_...

Page 11: ...full detail The wiring column indicates what kind of strap option is used on the pin A wiring of pull up means a pull up 2 2K to VCC is wired A wiring of pull down means a pull down 2 2K to GND is wired A wiring of nc means that pin has no strapping resistor connected to it Table 2 PHY 1 Power Up Strap Options Strap Function Pin Pin Wiring Value Setting Note PHYAD0 COL 42 nc 1 PHYADDR 1 default PH...

Page 12: ...ons Strap Function Pin Pin Wiring Value Setting Note PHYAD0 COL 42 nc 1 PHYADDR 3 PHYAD1 RXD_3 43 pull up 1 PHYAD2 4 RXD_2 _0 44 46 nc 000 AN_EN LED_LINK 28 nc 1 Autoneg enable Note LED must be wired to VCC AN1 LED_SPEED 27 nc 1 all modes AN0 LED_ACT 26 nc 1 CLK_OUT_EN GPIO1 21 pull up 1 enable clock output FX_EN_Z RX_ER 41 nc 1 disable FX mode LED_CFG CRS 40 nc 1 mode1 MII_MODE RX_DV 39 pull up 1...

Page 13: ...n MDC clock of up to 25MHz The PHYs support a so called broadcast function when commands are sent to the PHY address 31 which then will be accepted by both PHYs at the same time The PHYs can be individually addressed using the following MDIO addresses Table 4 PHY MDIO Addresses MDIO Address PHY 1 Port 0 Left RJ45 Connector J5 3 Port 1 Right RJ45 Connector J6 31 Broadcast to both PHYs Writes a regi...

Page 14: ...QSH QTH series The default mating connector is the ASP 122952 02 The ASP 122952 01 connector can plug directly into hosts with QSH 060 01 L D DP or QSH 060 01 L D connectors with the DP version having slightly better signal integrity Figure 7 Samtec ASP 122952 01 7 1 HSMC Connector Pin out Table Table 4 shows for every pin of the HSMC connector on the board and the corresponding PHY signal The sig...

Page 15: ...rxd 1 _0 60 61 rxd 0 _0 62 63 3 3 V 12 V 64 65 txen_1 rxcol_1 66 67 rxcrs_1 68 69 3 3 V 12 V 70 71 txd 1 _1 rxerr_1 72 73 txd 0 _1 rxdv_1 74 75 3 3 V 12 V 76 77 rxd 1 _1 78 79 reset_n rxd 0 _1 80 81 3 3 V 12 V 82 83 led_link_0 gpio4_0 84 85 led_link_1 gpio4_1 86 87 3 3 V 12 V 88 89 gpio8_0 90 91 gpio8_1 intn_1 92 93 3 3 V 12 V 94 95 clk_out_1 96 97 98 99 3 3 V 12 V 100 101 HSMC BANK 3 102 103 104 ...

Page 16: ...36 137 138 139 genio 0 140 141 3 3 V 12 V 142 143 genio 3 genio 1 144 145 genio 4 genio 2 146 147 3 3 V 12 V 148 149 otp 2 otp 0 150 151 otp 3 otp 1 152 153 3 3 V 12 V 154 155 otpclk 156 157 158 159 3 3 V PSNTn gnd 160 Notes PSNTn is wired to GND on the daughter board presence detect Only the 3 3V power pins are used The 12V pins are left unconnected ...

Page 17: ...Management clock input The device supports up to 25MHz standard is 2 5 MHz Note only one MDIO interface is available and all PHY devices communicate through this single interface using different MDIO addresses mdio inout Management data input output A 1 5K resistor to VCC is wired to it on the daughter board RMII Parallel MAC Interface PHY 1 rxclk_0 out 50 MHz RMII reference clock from PHY 1 rxcol...

Page 18: ... 4x2 connector clk_out_0 out Clock output clk_out from PHY 1 This is the 1588 synchronized reference clock 25MHz clk_out_1 out Clock output clk_out from PHY 2 This is the 1588 synchronized reference clock 25MHz Status Interrupt led_link _0 1 out Active low indication when the link is operable intn_0 1 out Interrupt active low from PHY PSTNn pin wired to GND on the daughter board Used as presence d...

Page 19: ...nce Guide V1 0 October 2013 19 8 PLCC 44 Socket The PLCC 44 Socket allows mounting of an optional OTP device for special purposes The device has several I O pins wired to the HMSC connector and operates with 3 3V power supplies Figure 8 PLCC 44 Top View ...

Page 20: ... O to HSMC otp 3 7 G 29 I O to HSMC otp 2 8 G 30 I O to HSMC otp 1 9 G 31 I O to HSMC otp 0 10 GND 32 GND 11 G 33 CLK to HSMC otpclk 12 G 34 G 13 G 35 VCC 3 3V supply 14 VCC 3 3V supply 36 G 15 G 37 G 16 VCC 3 3V supply 38 G 17 G 39 G 18 G 40 G 19 G 41 G 20 G 42 G 21 GND 43 GND 22 G 44 G Notes VCC is 3 3V supply voltage GND is 0V supply ground G pins are connected to GND These are unused I O pins ...

Page 21: ...5 31 32 AR2 C2 F38 AD34 33 MDIO MDC 34 AG30 H36 35 FPGA_3V3_JTAG_TCK FPGA_3V3_JTAG_TMS 36 37 HMSC_3V3_JTAG_TDO FPGA_3V3_JTAG_TDO 38 G22 AN22 39 ref_clk_x1 rxclk_0 40 W37 V37 D22 AR22 41 intn_0 42 AT22 F22 A22 AT21 43 txen_0 clk_out_0 44 AP22 B22 45 3 3 V 12 V 46 G33 AA33 47 txd 1 _0 rxcol_0 48 AE37 J39 G32 AB33 49 txd 0 _0 rxcrs_0 50 AE36 J38 51 3 3 V 12 V 52 J32 Y27 53 rxerr_0 54 AE39 K38 J31 AA2...

Page 22: ...1 109 110 AF36 N35 111 3 3 V 12 V 112 L34 AB32 113 114 AG36 K39 L33 AB31 115 116 AG35 L39 117 3 3 V 12 V 118 P27 AC34 119 120 AH37 R37 R27 AC33 121 122 AH36 R36 123 3 3 V 12 V 124 N34 AD32 125 126 AJ37 M39 N33 AD31 127 128 AJ36 M38 129 3 3 V 12 V 130 P34 AC30 131 132 AK36 N39 P33 AD30 133 134 AK35 P39 135 3 3 V 12 V 136 R33 AB26 137 138 AL39 T35 R32 AC27 139 genio 0 140 AL38 T34 141 3 3 V 12 V 142...

Page 23: ...acement options setting Table 9 HSMC Interface Signals Cyclone III Starter Kit Board FPGA Pin HSMC Pin Function Bank No Function HSMC Pin FPGA Pin 1 HSMC BANK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 E1 33 MDIO MDC 34 F3 35 FPGA_3V3_JTAG_TCK FPGA_3V3_JTAG_TMS 36 37 HMSC_3V3_JTAG_TDO FPGA_3V3_JTAG_TDO 38 A1 39 ref_clk_x1 rxclk_0 40 A9 H6 41 intn_0 42 D3...

Page 24: ... 98 F18 99 3 3 V 12 V 100 M2 101 102 P2 M1 103 104 P1 105 3 3 V 12 V 106 R2 107 108 T3 R1 109 110 R3 111 3 3 V 12 V 112 E17 113 114 G17 E18 115 116 G18 117 3 3 V 12 V 118 H17 119 120 K18 H18 121 122 L18 123 3 3 V 12 V 124 L17 125 126 L16 M18 127 128 M17 129 3 3 V 12 V 130 L14 131 132 L13 L15 133 134 M14 135 3 3 V 12 V 136 P17 137 138 R17 P18 139 genio 0 140 R18 141 3 3 V 12 V 142 R5 143 genio 3 ge...

Page 25: ...Dual DP83640 Ethernet PHY HSMC Daughter Board Reference Guide V1 0 October 2013 25 11 References 1 DP83640 Precision PHYTER IEEE 1588 Precision Time Protocol Transceiver National Semiconductor ...

Page 26: ... www morethanip com Europe Muenchner Str 199 D 85757 Karlsfeld Germany Tel 49 0 8131 333939 0 FAX 49 0 8131 333939 1 Nine Ways Research Development Ltd E Mail pbates nineways co uk Internet www nineways co uk UK Unit G 15 iDCentre Lathkill House rtc Business Park London Road Derby DE24 8UP United Kingdom Tel 44 0 1332 258847 FAX 44 0 1332 258823 ...

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