Dual DP83640 Ethernet PHY HSMC Daughter Board
Reference Guide
V1.0 - October 2013
18
rxcrs_0 (crs_dv)
out
Receive carrier sense/data valid indication from PHY 2.
rxd[1:0]_0
out
RMII receive data
rxdv_0
out
receive data valid from PHY 2
rxer_0
out
receive error indication from PHY 2
txd[1:0]_0
in
transmit data to PHY 2
txen_0
in
transmit enable to PHY 2
GPIO / 1588
gpio8 _0/1
in/out
General Purpose I/O8 at PHY
gpio4 _0/1
in/out
General Purpose I/O4 at PHY
Note this I/O is wired in parallel to the on-board 4x2
connector.
clk_out_0
out
Clock output (clk_out) from PHY 1. This is the 1588
synchronized reference clock (25MHz).
clk_out_1
out
Clock output (clk_out) from PHY 2. This is the 1588
synchronized reference clock (25MHz).
Status / Interrupt
led_link _0/1
out
Active low indication when the link is operable.
intn_0/1
out
Interrupt (active low) from PHY.
PSTNn
--
pin wired to GND on the daughter board. Used as presence
detect by the main board.
Spare I/O
genio[0,1,2,3,4]
in/out
General I/O available for arbitrary use.
The pins are available on a 5x2 connector.
PLCC-44 Socket I/O
otp[0,1,2,3]
in/out
General I/O connected to the PLCC-44 connector for
interfacing with an optional OTP device.
otpclk
in
Clock input to OTP device.
