6.5 Electrical Characteristics: Voltage Output (continued)
at 1.7 V ≤ V
DD
≤ 5.5 V, DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (R
L
=
5 kΩ to AGND) and capacitive load (C
L
= 200 pF to AGND), digital inputs at VDD or AGND, and all minimum and maximum
specifications at –40°C ≤ T
A
≤ +125°C and typical specifications at T
A
= 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power supply rejection ratio
(dc)
Internal V
REF
, gain = 2x, DAC at midscale,
V
DD
= 5 V ±10%
0.25
mV/V
DYNAMIC PERFORMANCE
t
sett
Output voltage settling time
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to
10%FSR, V
DD
= 5.5 V
20
µs
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to
10%FSR, V
DD
= 5.5 V, internal V
REF
, gain = 4x
25
Slew rate
V
DD
= 5.5 V
0.3
V/µs
Power-on glitch magnitude
At startup (DAC output disabled)
75
mV
At startup (DAC output disabled), R
L
= 100 kΩ
200
Output-enable glitch
magnitude
DAC output disabled to enabled (DAC registers at zero
scale), R
L
= 100 kΩ
250
mV
V
n
Output noise voltage (peak to
peak)
f = 0.1 Hz to 10 Hz, DAC at midscale, V
DD
= 5.5 V
50
µV
PP
Internal V
REF
, gain = 4x, f = 0.1 Hz to 10 Hz,
DAC at midscale, V
DD
= 5.5 V
90
Output noise density
f = 1 kHz, DAC at midscale, V
DD
= 5.5 V
0.35
µV/√Hz
Internal V
REF,
gain = 4x, f = 1 kHz, DAC at midscale,
V
DD
= 5.5 V
0.9
Power supply rejection ratio
(ac)
Internal V
REF
, gain = 4x, 200-mV 50-Hz or 60-Hz sine
wave superimposed on power supply voltage, DAC at
midscale
-68
dB
Code change glitch impulse
±1-LSB change around midscale (including
feedthrough)
10
nV-s
Code change glitch impulse
magnitude
±1-LSB change around midscale (including
feedthrough)
15
mV
POWER
I
DD
Current flowing into VDD
Normal operation, DACs at full scale, digital pins static,
external reference at V
DD
but the VREF pin is not
shorted to VDD
150
µA/ch
(1)
Measured with DAC output unloaded. For external reference and internal reference V
DD
≥ 1.21 x gain + 0.2 V, between end-point
codes: 32d to 4064d for 12-bit resolution, 8d to 1016d for 10-bit resolution.
(2)
Specified by design and characterization, not production tested.
(3)
Specified with 200-mV headroom with respect to reference value when internal reference is used.
(4)
Measured with DAC output unloaded.
(5)
The total power consumption is calculated by I
DD
x (total number of channels powered on) + (sleep-mode current).
(6)
When a DAC channel is configured in IOUT mode for long term and then switched to VOUT mode, the VOUT mode can show
parametric drift.
SLASF47 – MAY 2022
6
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