6
Configuring the Board
Configuring the Board
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opens a popup window displaying all the possible selections of those dividers. Care must be taken in
choosing these dividers, along with the VCO, charge pump and loop filter, such that the on-chip PLL of
the CDCE62005 can operate in a stable closed-loop manner. Refer to the CDCE62005 data sheet for
further information on appropriate configuration of the PLL for closed-loop operation. After the dividers
are set accordingly, the PLL LOCK indicator display on the EVMCS are a bright green color. Also, the
on-board LED D33 illuminates to indicate PLL lock. The output dividers for each output can also be
chosen from possible selections displayed in the popup window, opened by clicking the output-divider
tab in the EVMCS. Each output divider can also be disabled.
8.
Write to CDCE62005 EEPROM
To write any particular setting to the EEPROM (locked or unlocked), the menu item at the top of the
EVMCS titled “Tool” must be clicked. This highlights the items “Write EEPROM Unlocked” and “Write
EEPROM Locked” as part of a drop-down menu. Choosing the appropriate one after setting the desired
PLL configurations writes to the EEPROM in its appropriate mode.
Figure 10. Tools – Write to EEPROM
Configuration for Programming and Testing (with USB cable attached) (Default Configuration)
The CDCE62005EVM is configured by default to operate with the USB cable attached and a 3.3V power
supply added to EXT VDD and GND. In this configuration the USB microcontroller is powered by the USB
port 5V supply, while the CDCE62005 is powered by the 3.3V external supply. This configuration is best
for programming the CDCE62005 while also taking measurements. This configuration removes the power
variation found in USB power supplies by isolating the CDCE62005 from the USB supply.
Configuration for Programming (using USB power)
The CDCE62005EVM can use power supplied through the USB cable as its sole power source. (Not
recommended for measurements) This capability is intended for saving configuration settings to the
CDCE62005 and later powering the device from its internal memory (useful during performance testing of
the device). In this configuration JP_3_3 must be moved from its default position to the new position
shown below. Also the “Enable EVM Power” box must be checked on the EVM display.
Configuration for On-board Reference Input Biasing
If the CDCE62005 on-chip biasing is not used for AC-coupled reference input signals for PRI_REF or
SEC_REF, the CDCE62005EVM can alternately be set up to provide on-board biasing for LVPECL or
LVDS inputs. These bias voltages of 1.2V for LVDS and 1.9V for LVPECL are derived from the on-board
voltage regulator (U3). The bias points are available for every leg of the differential signals at both
PRI_REF and SEC_REF and can be enabled by using the jumpers on the CDCE62005EVM, JP_3_4 and
JP_3_5 for PRI_REF and JP_3_6 and JP_3_7 for SEC_REF. Each of these jumpers can be configured as
shown below for either LVPECL or LVDS bias.
8
Low Phase Noise Clock Evaluation Module — up to 1.5 GHz
SCAU024 – September 2008
