Texas Instruments CDCE62005EVM, User Manual

Page: 13 / 17

VCC_IN
VCC_IN
VCC_VCO
VCCA
VCC_OUT
VCC_VCO
VCC_PLL
VCC_PLL
VCC_PLL VCC_PLL
VCC_IN
VCC_OUT VCC_OUT
VCC_OUT
VCC_OUT
YP0 YN0 YP2 YN2 YP4 YN4 YP1 YN1 YP3 YN3
PRI_REFP PRI_REFN SEC_REFP SEC_REFN
SPI_CLK SPI_MOSI SPI_MISO SPI_LE MODE_SEL
TEST
OUT
A
VBB
PLL_LOCK
RESET_
PD_
AUX_IN EXT_LFP EXT_LFN
REF_SEL
TEST
OUT
A
PAD
R
VCC_OUT
C
AUXOUT
61.44MHzFilter
C82
10uF/6.3V
C82
10uF/6.3V
C154 0.1uF C154 0.1uF
C145 0.1uF C145 0.1uF
1
2
L5
BLM15HD102SN1D
L5
BLM15HD102SN1D
C162 0.1uF C162 0.1uF
C156 0.1uF C156 0.1uF
TESTO UTA
30
VCC_AUXIN
44
VCC_AUXOUT
15
VCC2_PLL
39
VCC6
8
U0N
28
U0P
27
VCC5
1
1
U1N
20
U1P
19
VCC4
18
U2N
17
U2P
16
VCC3
21
SPI_MISO
22
MODE_SEL
33
POWER_DOWN
12
AUX_OUT
13
VCC0
26
U3N
10
U3P
9
VCC2
29
U4N
7
U4P
6
VCC1
32
REG_CAP2
38
GND_VCO
36
VCC_VCO
34
REF_SEL
31
SPI_CLK
24
SPI_LE
25
SPI_MOSI
23
REG_CAP1
4
RESET
14
VCC1_PLL
5
VCC2_PLL
42
3
SEC_REF-
2
VCC_IN
1
45
PRI_REF-
46
VCC_IN
47
VBB
48
EXT_LFP
40
AUX_IN
43
EXT_LFN
41
PLL_LOCK
37
VCC_VCO
35
THERMAL_P AD
49
U5
CDCE62005
U5 CDCE62005
C155 0.1uF C155 0.1uF
C150
0.1uF-NP
C150
0.1uF-NP
C157
0.1uF
C157
0.1uF
1 2
R133
0
R133
0
IN
1
GND4
7
OUT
5
GND3
8
GND2
4
GND1
3
GND5
6
GND
2
U13
XtalFltr61.44Mhz
U13
XtalFltr61.44Mhz
C148 0.1uF C148 0.1uF
C151 0.1uF C151 0.1uF
C152 0.1uF C152 0.1uF
C161
0.1uF
C161
0.1uF
C160 0.1uF C160 0.1uF
2
3
1
4
5
J46
SMA-EDGE
J46
SMA-EDGE
C158 0.1uF C158 0.1uF
1
2
R141
50
R141
50
C144 0.1uF C144 0.1uF
1 2
R94
0
R94
0
C159 0.1uF C159 0.1uF C141 0.1uF C141 0.1uF
C149 0.1uF C149 0.1uF
C142 0.1uF C142 0.1uF
C75 2.2uF C75 2.2uF
C163 0.1uF C163 0.1uF
C83 10uF/6.3V C83 10uF/6.3V 1 2
R134 0 R134 0
C147 0.1uF C147 0.1uF
1
2
R95
100
R95
100
C146 0.1uF C146 0.1uF
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CDCE62005EVM Board Schematic Diagram
SCAU024 – September 2008 Low Phase Noise Clock Evaluation Module — up to 1.5 GHz 13
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