Texas Instruments CDCE62005EVM, User Manual

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VCC_OUT VCC_OUT VCC_OUT VCC_OUT VCC_OUT
YP0 YN0 YP1 YN1 YP2 YN2 YP3 YN3 YP4 YN4
Y0_150_TERM Y1_150_TERM Y2_150_TERM Y3_150_TERM Y4_150_TERM
YP0 YN0 YP1 YN1 YP2 YN2 YP3 YN3 YP4 YN4
OUTPUTCLOCKS
YP0 YN0 YP1 YN1 YP2 YN2 YP3 YN3 YP4
YN4
1
2
R218
150
R218
150
2
3
1
4
5
J45
SMA-EDGE
J45
SMA-EDGE
1
2
R217
10k
R217
10k
2
3
1
4
5
J36
SMA-EDGE
J36
SMA-EDGE
1
2
R231
150
R231
150
2
3
1
4
5
J39
SMA-EDGE
J39
SMA-EDGE
2
3
1
4
5
J43
SMA-EDGE
J43
SMA-EDGE
Q55
FDV303N
Q55
FDV303N
1
2
R226
150
R226
150
1 2
R220 0-NP R220 0-NP
Q58
FDV303N
Q58
FDV303N
Q54
FDV303N
Q54
FDV303N
2
3
1
4
5
J48
SMA-EDGE
J48
SMA-EDGE
Q62
FDV303N
Q62
FDV303N
1 2
R224 0-NP R224 0-NP
Q60
FDV303N
Q60
FDV303N
1 2
R214 0-NP R214 0-NP
2
3
1
4
5
J35
SMA-EDGE
J35
SMA-EDGE
1
2
R216
150
R216
150
1 2
R234 0-NP R234 0-NP
C120 0.1uF C120 0.1uF
1
2
R223
150
R223
150
1 2
R229 0-NP R229 0-NP
C1
19
0.1uF C1
19
0.1uF
1
2
R213
150
R213
150
Q56
FDV303N
Q56
FDV303N
1
2
R222
10k
R222
10k
C131 0.1uF C131 0.1uF
Q57
FDV303N
Q57
FDV303N
C130 0.1uF C130 0.1uF
1 2
R225 0-NP R225 0-NP
2
3
1
4
5
J49
SMA-EDGE
J49
SMA-EDGE
1
2
R212
10k
R212
10k
C88 0.1uF C88 0.1uF
1 2
R215 0-NP R215 0-NP
C87 0.1uF C87 0.1uF C90 0.1uF C90 0.1uF
Q45
FDV303N
Q45
FDV303N
1
2
R233
150
R233
150
1
2
R232
10k
R232
10k
2
3
1
4
5
J34
SMA-EDGE
J34
SMA-EDGE
C86 0.1uF C86 0.1uF
1 2
R219 0-NP R219 0-NP
1
2
R228
150
R228
150
1
2
R227
10k
R227
10k
Q61
FDV303N
Q61
FDV303N
1 2
R235 0-NP R235 0-NP
2
3
1
4
5
J32
SMA-EDGE
J32
SMA-EDGE
Q59
FDV303N
Q59
FDV303N
1
2
R221
150
R221
150
C89 0.1uF C89 0.1uF C84 0.1uF C84 0.1uF
1 2
R230 0-NP R230 0-NP
2
3
1
4
5
J41
SMA-EDGE
J41
SMA-EDGE
1
2
R21
1
150
R21
1
150
CDCE62005EVM Board Schematic Diagram
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Low Phase Noise Clock Evaluation Module — up to 1.5 GHz 12 SCAU024 – September 2008
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