Texas Instruments CDCE62005EVM, User Manual

Page: 14 / 17

L
VPECL_BIAS
L
VPECL_BIAS
L
VPECL_BIAS
L
VPECL_BIAS
L
VDS_BIAS
L
VDS_BIAS
L
VDS_BIAS
L
VDS_BIAS
+3V3
PRI_REFN PRI_REFP
SEC_REFN SEC_REFP
AUX_IN
OSC_EN
PRI_REFN PRI_REFP
INPUTCLOCKPRI
INPUTCLOCKSEC
LAYOUTCritical
AUXIN
SEC_REFN SEC_REFP
PRI_REFP
PRI_REFN
L
VDS
BIAS
L
VDS
L
VPECL
L
VPECL
BIAS
BIAS
BIAS
L
VDS
L
VDS
L
VPECL
L
VPECL
2
3
1
4
5
J104
SMA-EDGE
J104
SMA-EDGE
1
2
R136
49.9
R136
49.9
C71 1uF C71 1uF
1 2
R137 49.9 R137 49.9
C85
5pf-NP
C85
5pf-NP
C65 1uF C65 1uF
1
3
2
JP_3_7JP_3_7
C67 1uF C67 1uF
C76 0.1uF C76 0.1uF
C36 1uF C36 1uF
C69 1uF C69 1uF
1
3
2
JP_3_4JP_3_4
C50 1uF C50 1uF
C57 1uF C57 1uF
C80 0.1uF C80 0.1uF
OE
1
VCC
6
NC/OUTN
5
OUT/OUTP
4
GND
3
NC
2
U12
PE7745DU-30.72M
U12
PE7745DU-30.72M
C77 0.1uF C77 0.1uF
C58 1uF C58 1uF
1 2
R130 49.9 R130 49.9
C78 0.1uF C78 0.1uF
1
3
2
JP_3_6JP_3_6
1
2
L9
BLM15HD102SN1D
L9
BLM15HD102SN1D
1 2
R132 49.9 R132 49.9
1
2
R65
100k-NP
R65
100k-NP
C66 1uF C66 1uF
2
3
4
5
1
J213
SMA-VER
T
J213
SMA-VER
T
C79 0.1uF C79 0.1uF
1
2
R135
49.9-NP
R135
49.9-NP
2
3
1
4
5
J103
SMA-EDGE
J103
SMA-EDGE
1 2
R131 49.9 R131 49.9
1
3
2
JP_3_5JP_3_5
2
3
1
4
5
J203
SMA-EDGE
J203
SMA-EDGE
1
2 3
4 5
6
25.00MhzCrystal Crystal25.00MHz 25.00MhzCrystal Crystal25.00MHz
2
3
1
4
5
J204
SMA-EDGE
J204
SMA-EDGE
CDCE62005EVM Board Schematic Diagram
www.ti.com
Low Phase Noise Clock Evaluation Module — up to 1.5 GHz 14 SCAU024 – September 2008
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