ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554H – MAY 2009 – REVISED SEPTEMBER 2013
www.ti.com
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
Voltage applied at DVCC and AVCC pins to V
SS
–0.3 V to 4.1 V
–0.3 V to (V
CC
+ 0.3 V),
Voltage applied to any pin (excluding VCORE, RF_P, RF_N, and R_BIAS)
(2)
4.1 V Max
Voltage applied to VCORE, RF_P, RF_N, and R_BIAS
(2)
–0.3 V to 2.0 V
Input RF level at pins RF_P and RF_N
10 dBm
Diode current at any device terminal
±2 mA
Storage temperature range
(3)
, T
stg
–55°C to 150°C
Maximum junction temperature, T
J
95°C
(1)
Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating
Conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
All voltages referenced to V
SS
.
(3)
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
Thermal Packaging Characteristics CC430F51xx
Low-K board
48 QFN (RGZ)
98°C/W
θ
JA
Junction-to-ambient thermal resistance, still air
High-K board
48 QFN (RGZ)
28°C/W
Thermal Packaging Characteristics CC430F61xx
Low-K board
64 QFN (RGC)
83°C/W
θ
JA
Junction-to-ambient thermal resistance, still air
High-K board
64 QFN (RGC)
26°C/W
Recommended Operating Conditions
Typical values are specified at V
CC
= 3.3 V and T
A
= 25°C (unless otherwise noted)
MIN
NOM
MAX
UNIT
Supply voltage range applied at all DVCC and AVCC
PMMCOREVx = 0
1.8
3.6
pins
(1)
during program execution and flash programming
(default after POR)
V
CC
V
with PMM default settings, Radio is not operational with
PMMCOREVx = 1
2.0
3.6
PMMCOREVx = 0 or 1
(2) (3)
Supply voltage range applied at all DVCC and AVCC
PMMCOREVx = 2
2.2
3.6
V
CC
pins
(1)
during program execution, flash programming, and
V
PMMCOREVx = 3
2.4
3.6
radio operation with PMM default settings
(2) (3)
Supply voltage range applied at all DVCC and AVCC
pins
(1)
during program execution, flash programming and
PMMCOREVx = 2,
V
CC
radio operation with PMMCOREVx = 2, high-side SVS
SVSHRVLx = SVSHRRRLx = 1
2.0
3.6
V
level lowered (SVSHRVL = SVSMHRRL = 1) or high-side
or SVSHE = 0
SVS disabled (SVSHE = 0)
(2) (3) (4)
Supply voltage applied at the exposed die attach VSS and
V
SS
0
V
AVSS pin
T
A
Operating free-air temperature
–40
85
°C
T
J
Operating junction temperature
–40
85
°C
C
VCORE
Recommended capacitor at VCORE
(5)
470
nF
C
DVCC
/
Capacitor ratio of capacitor at DVCC to capacitor at
10
C
VCORE
VCORE
(1)
It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
(2)
Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
(3)
The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the
PMM, SVS High Side
threshold
parameters for the exact values and further details.
(4)
Lowering the high-side SVS level or disabling the high-side SVS might cause the LDO to operate out of regulation, but the core voltage
will still stay within its limits and is still supervised by the low-side SVS ensuring reliable operation.
(5)
A capacitor tolerance of ±20% or better is required.
40
Submit Documentation Feedback
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links:
CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137
CC430F5135 CC430F5133
