ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
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SLAS554H – MAY 2009 – REVISED SEPTEMBER 2013
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 4. Interrupt Sources, Flags, and Vectors
SYSTEM
WORD
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
INTERRUPT
ADDRESS
System Reset
Power-Up
External Reset
WDTIFG, KEYV (SYSRSTIV)
(1) (2)
Reset
0FFFEh
63, highest
Watchdog Timeout, Password
Violation
Flash Memory Password Violation
System NMI
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
PMM
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,
(Non)maskable
0FFFCh
62
Vacant Memory Access
JMBOUTIFG (SYSSNIV)
(1) (3)
JTAG Mailbox
User NMI
NMI
NMIIFG, OFIFG, ACCVIFG (SYSUNIV)
(1) (3)
(Non)maskable
0FFFAh
61
Oscillator Fault
Flash Memory Access Violation
Comparator_B
Comparator_B Interrupt Flags (CBIV)
(1)
Maskable
0FFF8h
60
Watchdog Interval Timer Mode
WDTIFG
Maskable
0FFF6h
59
USCI_A0 Receive or Transmit
UCA0RXIFG, UCA0TXIFG (UCA0IV)
(1)
Maskable
0FFF4h
58
UCB0RXIFG, UCB0TXIFG, I2C Status Interrupt
USCI_B0 Receive or Transmit
Maskable
0FFF2h
57
Flags (UCB0IV)
(1)
ADC12_A
ADC12IFG0 ... ADC12IFG15 (ADC12IV)
(1)
Maskable
0FFF0h
56
(Reserved on CC430F612x)
TA0
TA0CCR0 CCIFG0
Maskable
0FFEEh
55
TA0CCR1 CCIFG1 ... TA0CCR4 CCIFG4,
TA0
Maskable
0FFECh
54
TA0IFG (TA0IV)
(1)
Radio Interface Interrupt Flags (RF1AIFIV)
RF1A CC1101-based Radio
Maskable
0FFEAh
53
Radio Core Interrupt Flags (RF1AIV)
DMA
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)
(1)
Maskable
0FFE8h
52
TA1
TA1CCR0 CCIFG0
Maskable
0FFE6h
51
TA1CCR1 CCIFG1 ... TA1CCR2 CCIFG2,
TA1
Maskable
0FFE4h
50
TA1IFG (TA1IV)
(1)
I/O Port P1
P1IFG.0 to P1IFG.7 (P1IV)
(1)
Maskable
0FFE2h
49
I/O Port P2
P2IFG.0 to P2IFG.7 (P2IV)
(1)
Maskable
0FFE0h
48
LCD_B
LCD_B Interrupt Flags (LCDBIV)
(1)
Maskable
0FFDEh
47
(Reserved on CC430F513x)
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RTC_A
Maskable
0FFDCh
46
RT0PSIFG, RT1PSIFG (RTCIV)
(1)
AES
AESRDYIFG
Maskable
0FFDAh
45
0FFD8h
44
Reserved
Reserved
(4)
⋮
⋮
0FF80h
0, lowest
(1)
Multiple source flags
(2)
A reset is generated if the CPU tries to fetch instructions from within peripheral space.
(3)
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(4)
Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain
compatibility with other devices, it is recommended to reserve these locations.
Copyright © 2009–2013, Texas Instruments Incorporated
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