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ECCN 5E002 TSPA - Technology / Software Publicly Available

CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133

SLAS554H – MAY 2009 – REVISED SEPTEMBER 2013

www.ti.com

Table 9. Port Mapping, Mnemonics and Functions (continued)

OUTPUT PIN FUNCTION

VALUE

PxMAPy MNEMONIC

INPUT PIN FUNCTION (PxDIR.y = 0)

(PxDIR.y = 1)

Reserved

None

DVSS

Reserved

None

DVSS

Reserved

None

DVSS

Reserved

None

DVSS

Disables the output driver as well as the input Schmitt-trigger to prevent

31 (0FFh)

(6)

PM_ANALOG

parasitic cross currents when applying analog signals.

(6)

The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored
resulting in a read out value of 31.

Table 10. Default Mapping

INPUT PIN FUNCTION

OUTPUT PIN FUNCTION

PIN

PxMAPy MNEMONIC

(PxDIR.y = 0)

(PxDIR.y = 1)

P1.0/P1MAP0

PM_RFGDO0

None

Radio GDO0

P1.1/P1MAP1

PM_RFGDO2

None

Radio GDO2

USCI_B0 SPI slave out master in (direction controlled by USCI),

P1.2/P1MAP2

PM_UCB0SOMI/PM_UCB0SCL

USCI_B0 I2C clock (open drain and direction controlled by USCI)

USCI_B0 SPI slave in master out (direction controlled by USCI),

P1.3/P1MAP3

PM_UCB0SIMO/PM_UCB0SDA

USCI_B0 I2C data (open drain and direction controlled by USCI)

USCI_B0 clock input/output (direction controlled by USCI),

P1.4/P1MAP4

PM_UCB0CLK/PM_UCA0STE

USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)

USCI_A0 UART RXD (Direction controlled by USCI - input),

P1.5/P1MAP5

PM_UCA0RXD/PM_UCA0SOMI

USCI_A0 SPI slave out master in (direction controlled by USCI)

USCI_A0 UART TXD (Direction controlled by USCI - output),

P1.6/P1MAP6

PM_UCA0TXD/PM_UCA0SIMO

USCI_A0 SPI slave in master out (direction controlled by USCI)

USCI_A0 clock input/output (direction controlled by USCI),

P1.7/P1MAP7

PM_UCA0CLK/PM_UCB0STE

USCI_B0 SPI slave transmit enable (direction controlled by USCI - input)

P2.0/P2MAP0

PM_CBOUT1/PM_TA1CLK

TA1 clock input

Comparator_B output

P2.1/P2MAP1

PM_TA1CCR0A

TA1 CCR0 capture input CCI0A

TA1 CCR0 compare output Out0

P2.2/P2MAP2

PM_TA1CCR1A

TA1 CCR1 capture input CCI1A

TA1 CCR1 compare output Out1

P2.3/P2MAP3

PM_TA1CCR2A

TA1 CCR2 capture input CCI2A

TA1 CCR2 compare output Out2

P2.4/P2MAP4

PM_RTCCLK

None

RTCCLK output

P2.5/P2MAP5

PM_SVMOUT

None

SVM output

P2.6/P2MAP6

PM_ACLK

None

ACLK output

P2.7/P2MAP7

PM_ADC12CLK/PM_DMAE0

DMA external trigger input

ADC12CLK output

P3.0/P3MAP0

PM_CBOUT0/PM_TA0CLK

TA0 clock input

Comparator_B output

P3.1/P3MAP1

PM_TA0CCR0A

TA0 CCR0 capture input CCI0A

TA0 CCR0 compare output Out0

P3.2/P3MAP2

PM_TA0CCR1A

TA0 CCR1 capture input CCI1A

TA0 CCR1 compare output Out1

P3.3/P3MAP3

PM_TA0CCR2A

TA0 CCR2 capture input CCI2A

TA0 CCR2 compare output Out2

P3.4/P3MAP4

PM_TA0CCR3A

TA0 CCR3 capture input CCI3A

TA0 CCR3 compare output Out3

P3.5/P3MAP5

PM_TA0CCR4A

TA0 CCR4 capture input CCI4A

TA0 CCR4 compare output Out4

P3.6/P3MAP6

PM_RFGDO1

None

Radio GDO1

P3.7/P3MAP7

PM_SMCLK

None

SMCLK output

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CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137

CC430F5135 CC430F5133

Summary of Contents for CC430F5133

Page 1: ...isters Detection Address Check Flexible Packet Hardware Real Time Clock RTC Length and Automatic CRC Handling Two Universal Serial Communication Support for Automatic Clear Channel Interfaces Assessme...

Page 2: ...ogrammable flash memory up to 4KB of RAM two 16 bit timers a high performance 12 bit analog to digital converter ADC with eight external inputs plus internal temperature and battery sensors on CC430F6...

Page 3: ...6 ch 30 48 RGZ 4 int ch 6 ext CC430F5133 8 2 5 3 n a 1 1 6 ch 30 48 RGZ 4 int ch 1 For the most current package and ordering information see the Package Option Addendum at the end of this document or...

Page 4: ...ncy Synthesizer CPU Interface Packet Handler Digital RSSI Carrier Sense PQI LQI CCA Sub 1GHz Radio CC1101 MPY32 ADC12 32kHz 26MHz Unified Clock System CPUXV2 incl 16 Registers JTAG Interface DMA Contr...

Page 5: ...S21 36 13 RF_XOUT P1 4 PM_UCB0CLK PM_UCA0STE S22 37 12 AVCC_RF DVCC 38 11 GUARD LCDCAP R33 45 4 PJ 0 TDO P1 5 PM_UCA0RXD PM_UCA0SOMI R23 46 3 PJ 1 TDI TCLK P1 6 PM_UCA0TXD PM_UCA0SIMO R13 LCDREF 47 2...

Page 6: ...equency Synthesizer CPU Interface Packet Handler Digital RSSI Carrier Sense PQI LQI CCA Sub 1GHz Radio CC1101 MPY32 32kHz 26MHz Unified Clock System JTAG Interface DMA Controller 3 Channel SYS Port Ma...

Page 7: ...B0CLK PM_UCA0STE S22 37 12 AVCC_RF DVCC 38 11 GUARD LCDCAP R33 45 4 PJ 0 TDO P1 5 PM_UCA0RXD PM_UCA0SOMI R23 46 3 PJ 1 TDI TCLK P1 6 PM_UCA0TXD PM_UCA0SIMO R13 LCDREF 47 2 PJ 2 TMS P1 7 PM_UCA0CLK PM_...

Page 8: ...igital RSSI Carrier Sense PQI LQI CCA Sub 1GHz Radio CC1101 MPY32 ADC12 32kHz 26MHz Unified Clock System JTAG Interface DMA Controller 3 Channel SYS Port Mapping Controller Watch dog REF Voltage Refer...

Page 9: ...M_SVMOUT CB5 A5 VREF VeREF AVCC P5 0 XIN P5 1 XOUT AVSS DVCC P1 0 PM_RFGDO0 P3 7 PM_SMCLK P3 6 PM_RFGDO1 P3 5 PM_TA0CCR4A P3 4 PM_TA0CCR3A P3 3 PM_TA0CCR2A P3 2 PM_TA0CCR1A P3 1 PM_TA0CCR0A P3 0 PM_CB...

Page 10: ...supply General purpose digital I O with port interrupt and mappable secondary function P1 4 PM_UCB0CLK 12 I O Default mapping USCI_B0 clock input output USCI_A0 SPI slave transmit enable PM_UCA0STE S2...

Page 11: ...put S4 General purpose digital I O P4 1 S3 32 I O LCD segment output S3 General purpose digital I O P4 0 S2 33 I O LCD segment output S2 General purpose digital I O P5 3 S1 34 I O LCD segment output S...

Page 12: ...al purpose digital I O with port interrupt and mappable secondary function Default mapping RTCCLK output P2 4 PM_RTCCLK CB4 Comparator_B input CB4 60 I O A4 VREF VeREF Analog input A4 12 bit ADC CC430...

Page 13: ...upt and mappable secondary function 11 I O PM_UCB0SCL Default mapping USCI_B0 SPI slave out master in UCSI_B0 I2C clock General purpose digital I O with port interrupt and mappable secondary function...

Page 14: ...ound supply for ADC12 General purpose digital I O P5 1 XOUT 43 I O Output terminal of crystal oscillator XT1 General purpose digital I O P5 0 XIN 44 I O Input terminal for crystal oscillator XT1 AVCC...

Page 15: ...the I Q signals are digitized Automatic gain control AGC fine channel filtering demodulation bit and packet synchronization are performed digitally The transmitter part is based on direct synthesis of...

Page 16: ...ange Each instruction can operate on word and byte data Operating Modes The CC430 has one active mode and five software selectable low power modes of operation An interrupt event can wake up the devic...

Page 17: ...12_A ADC12IFG0 ADC12IFG15 ADC12IV 1 Maskable 0FFF0h 56 Reserved on CC430F612x TA0 TA0CCR0 CCIFG0 Maskable 0FFEEh 55 TA0CCR1 CCIFG1 TA0CCR4 CCIFG4 TA0 Maskable 0FFECh 54 TA0IFG TA0IV 1 Radio Interface...

Page 18: ...128 B 128 B 00187Fh to 001800h 00187Fh to 001800h 00187Fh to 001800h 00187Fh to 001800h BSL 3 512 B 512 B 512 B 512 B 0017FFh to 001600h 0017FFh to 001600h 0017FFh to 001600h 0017FFh to 001600h BSL 2...

Page 19: ...Bi Wire interface Spy Bi Wire can be used to interface with MSP430 development tools and device programmers The Spy Bi Wire interface pin requirements are shown in Table 8 For further details on inter...

Page 20: ...ator VLO or the trimmed low frequency oscillator REFO Main clock MCLK the system clock used by the CPU MCLK can be sourced by same sources made available to ACLK Sub Main clock SMCLK the subsystem clo...

Page 21: ...ection controlled by USCI output 18 2 PM_UCA0SIMO USCI_A0 SPI slave in master out direction controlled by USCI PM_UCA0CLK USCI_A0 clock input output direction controlled by USCI 19 3 PM_UCB0STE USCI_B...

Page 22: ...AP5 PM_UCA0RXD PM_UCA0SOMI USCI_A0 SPI slave out master in direction controlled by USCI USCI_A0 UART TXD Direction controlled by USCI output P1 6 P1MAP6 PM_UCA0TXD PM_UCA0SIMO USCI_A0 SPI slave in mas...

Page 23: ...RITY SYSRSTIV System Reset 019Eh No interrupt pending 00h Brownout BOR 02h Highest RST NMI POR 04h DoBOR BOR 06h Reserved 08h Security violation BOR 0Ah SVSL POR 0Ch SVSH POR 0Eh SVML_OVP POR 10h SVMH...

Page 24: ...Reserved 15 Reserved Reserved Reserved 16 UCA0RXIFG UCA0RXIFG UCA0RXIFG 17 UCA0TXIFG UCA0TXIFG UCA0TXIFG 18 UCB0RXIFG UCB0RXIFG UCB0RXIFG 19 UCB0TXIFG UCB0TXIFG UCB0TXIFG 20 Reserved Reserved Reserved...

Page 25: ...erations AES128 Accelerator The AES accelerator module performs encryption and decryption of 128 bit data with 128 bit keys according to the Advanced Encryption Standard AES FIPS PUB 197 in hardware U...

Page 26: ...ACLK internal ACLK Timer NA SMCLK internal SMCLK RFCLK 192 1 INCLK PM_TA0CCR0A CCI0A PM_TA0CCR0A DVSS CCI0B CCR0 TA0 DVSS GND DVCC VCC PM_TA0CCR1A CCI1A PM_TA0CCR1A ADC12 internal 2 CBOUT internal CCI...

Page 27: ...timers that can be cascaded to form a 16 bit timer counter Both timers can be read and written by software Calendar mode integrates an internal calendar which compensates for months with less than 31...

Page 28: ...ples to be converted and stored without any CPU intervention Embedded Emulation Module EEM S Version The Embedded Emulation Module EEM supports real time in system debugging The S version of the EEM i...

Page 29: ...2 see Table 29 0200h 000h 01Fh Port P3 P4 see Table 30 0220h 000h 01Fh P4 not available on CC430F513x Port P5 see Table 31 0240h 000h 01Fh Port PJ see Table 32 0320h 000h 01Fh TA0 see Table 33 0340h 0...

Page 30: ...ET Flash control 1 FCTL1 00h Flash control 3 FCTL3 04h Flash control 4 FCTL4 06h Table 19 CRC16 Registers Base Address 0150h REGISTER DESCRIPTION REGISTER OFFSET CRC data input CRC16DI 00h CRC initial...

Page 31: ...STER OFFSET Port mapping key register PMAPKEYID 00h Port mapping control register PMAPCTL 02h Table 26 Port Mapping Port P1 Registers Base Address 01C8h REGISTER DESCRIPTION REGISTER OFFSET Port P1 0...

Page 32: ...or word P1IV 0Eh Port P1 interrupt edge select P1IES 18h Port P1 interrupt enable P1IE 1Ah Port P1 interrupt flag P1IFG 1Ch Port P2 input P2IN 01h Port P2 output P2OUT 03h Port P2 direction P2DIR 05h...

Page 33: ...1 TA0CCTL1 04h Capture compare control 2 TA0CCTL2 06h Capture compare control 3 TA0CCTL3 08h Capture compare control 4 TA0CCTL4 0Ah TA0 counter register TA0R 10h Capture compare register 0 TA0CCR0 12...

Page 34: ...REGISTER DESCRIPTION REGISTER OFFSET 16 bit operand 1 multiply MPY 00h 16 bit operand 1 signed multiply MPYS 02h 16 bit operand 1 multiply accumulate MAC 04h 16 bit operand 1 signed multiply accumula...

Page 35: ...tion address high DMA0DAH 08h DMA channel 0 transfer size DMA0SZ 0Ah Table 39 DMA Channel 1 Registers Base Address 0520h REGISTER DESCRIPTION REGISTER OFFSET DMA channel 1 control DMA1CTL 00h DMA chan...

Page 36: ...interrupt enable UCA0IE 1Ch USCI interrupt flags UCA0IFG 1Dh USCI interrupt vector word UCA0IV 1Eh Table 42 USCI_B0 Registers Base Address 05E0h REGISTER DESCRIPTION REGISTER OFFSET USCI synchronous...

Page 37: ...12MCTL8 18h ADC memory control register 9 ADC12MCTL9 19h ADC memory control register 10 ADC12MCTL10 1Ah ADC memory control register 11 ADC12MCTL11 1Bh ADC memory control register 12 ADC12MCTL12 1Ch AD...

Page 38: ...ccelerator data in register AESADIN 008h AES accelerator data out register AESADOUT 00Ah Table 46 LCD_B Registers Base Address 0A00h REGISTER DESCRIPTION REGISTER OFFSET LCD_B control register 0 LCDBC...

Page 39: ...12h Radio instruction word register 2 byte auto read RF1AINSTR2W 14h Radio data in register RF1ADINW 16h Radio status word register RF1ASTATW 20h Radio status word register 1 byte auto read RF1ASTAT1W...

Page 40: ...ly voltage range applied at all DVCC and AVCC PMMCOREVx 0 1 8 3 6 pins 1 during program execution and flash programming default after POR VCC V with PMM default settings Radio is not operational with...

Page 41: ...N NOM MAX UNIT PMMCOREVx 0 0 8 default condition PMMCOREVx 1 0 12 fSYSTEM Processor MCLK frequency 6 see Figure 2 MHz PMMCOREVx 2 0 16 PMMCOREVx 3 0 20 PINT Internal power dissipation VCC I DVCC W VCC...

Page 42: ...1 60 1 85 IAM RAM 5 RAM 3 0 V mA 2 0 21 0 24 1 20 1 80 2 40 2 70 3 0 22 0 25 1 30 1 90 2 50 3 10 3 60 1 All inputs are tied to 0 V or to VCC Outputs do not source or sink any current 2 The currents ar...

Page 43: ...aracterized with a Micro Crystal MS1V T1K crystal with a load capacitance of 12 5 pF The internal and external load capacitance are chosen to closely match the required 12 5 pF 3 Current for watchdog...

Page 44: ...icly Available CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137 CC430F5135 CC430F5133 SLAS554H MAY 2009 REVISED SEPTEMBER 2013 www ti com Typical Characteristics Low Power Mode Supply...

Page 45: ...re chosen to closely match the required 12 5 pF 3 Current for watchdog timer and RTC clocked by ACLK included ACLK low frequency crystal operation XTS 0 XT1DRIVEx 0 CPUOFF 1 SCG0 1 SCG1 1 OSCOFF 0 LPM...

Page 46: ...e VIN VSS or VCC 5 pF Ilkg Px y High impedance leakage current 1 2 1 8 V 3 V 50 nA Ports with interrupt capability External interrupt timing External trigger pulse see block diagram and t int 1 8 V 3...

Page 47: ...SS 0 25 1 8 V I OLmax 10 mA PxDS y 1 3 VSS VSS 0 60 Low level output voltage VOL V Full Drive Strength I OLmax 5 mA PxDS y 1 2 VSS VSS 0 25 3 V I OLmax 15 mA PxDS y 1 3 VSS VSS 0 60 VCC 1 8 V 16 PMMCO...

Page 48: ...C ECCN 5E002 TSPA Technology Software Publicly Available CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137 CC430F5135 CC430F5133 SLAS554H MAY 2009 REVISED SEPTEMBER 2013 www ti com Typ...

Page 49: ...Level Output Current mA VDD 5 5 V VCC 1 8 V P4 3 TA 25 C TA 85 C ECCN 5E002 TSPA Technology Software Publicly Available CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137 CC430F5135 CC4...

Page 50: ...lator pins XIN and XOUT d Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins e Use assembly materials and techniques that avoid any parasitic load on the oscillator XIN and XOUT...

Page 51: ...e Low Frequency Oscillator REFO over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT IREFO REFO oscillator...

Page 52: ...x 6 DCOx 0 MODx 0 4 6 10 7 MHz fDCO 6 31 DCO frequency 6 31 1 DCORSELx 6 DCOx 31 MODx 0 39 0 88 0 MHz fDCO 7 0 DCO frequency 7 0 1 DCORSELx 7 DCOx 0 MODx 0 8 5 19 6 MHz fDCO 7 31 DCO frequency 7 31 1...

Page 53: ...LPM Core voltage low current mode PMMCOREV 0 1 8 V DVCC 3 6 V 1 44 V PMM SVS High Side over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TE...

Page 54: ...MH on or off voltage level 1 SVMHE 1 SVSMHRRL 4 2 25 2 35 2 50 V SVMHE 1 SVSMHRRL 5 2 52 2 65 2 78 SVMHE 1 SVSMHRRL 6 2 85 3 00 3 15 SVMHE 1 SVSMHRRL 7 2 85 3 00 3 15 SVMHE 1 SVMHOVPE 1 3 75 SVMHE 1 d...

Page 55: ...n fMCLK 4 0 MHz 5 Wake up time from LPM2 LPM3 or tWAKE UP FAST where n 0 1 2 or 3 s LPM4 to active mode 1 fMCLK 4 0 MHz 6 SVSLFP 1 PMMCOREV SVSMLRRL n Wake up time from LPM2 LPM3 or tWAKE UP SLOW wher...

Page 56: ...e unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Internal SMCLK ACLK fTA Timer_A input clock frequency External TACLK 1 8 V 3 V 25 MHz Duty cycle 50 10 All capture inputs tTA ca...

Page 57: ...ating free air temperature unless otherwise noted see Note 1 Figure 15 and Figure 16 PARAMETER TEST CONDITIONS PMMCOREVx VCC MIN TYP MAX UNIT 1 8 V 55 0 ns 3 0 V 38 tSU MI SOMI input data setup time 2...

Page 58: ...y Available CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137 CC430F5135 CC430F5133 SLAS554H MAY 2009 REVISED SEPTEMBER 2013 www ti com Figure 15 SPI Master Mode CKPH 0 Figure 16 SPI M...

Page 59: ...time 2 4 V 2 3 ns 3 0 V 2 1 8 V 5 0 ns 3 0 V 5 tHD SI SIMO input data hold time 2 4 V 5 3 ns 3 0 V 5 1 8 V 76 0 ns 3 0 V 60 UCLK edge to SOMI valid tVALID SO SOMI output data valid time 2 CL 20 pF 2...

Page 60: ...CCN 5E002 TSPA Technology Software Publicly Available CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137 CC430F5135 CC430F5133 SLAS554H MAY 2009 REVISED SEPTEMBER 2013 www ti com Figure...

Page 61: ...rnal UCLK fSYSTEM MHz Duty cycle 50 10 fSCL SCL clock frequency 2 2 V 3 V 0 400 kHz fSCL 100 kHz 4 0 tHD STA Hold time repeated START 2 2 V 3 V s fSCL 100 kHz 0 6 fSCL 100 kHz 4 7 tSU STA Setup time f...

Page 62: ...LCDEXT 1 2 4 3 6 V external biasing charge pump disabled Capacitor on LCDCAP when LCDCPEN 1 VLCDx 0000 charge CLCDCAP 4 7 4 7 10 F charge pump enabled pump enabled fLCD 2 mux fFRAME with fFrame LCD fr...

Page 63: ...N 1 VLCDx 1001 2 0 V to 3 6 V 3 02 V LCDCPEN 1 VLCDx 1010 2 0 V to 3 6 V 3 08 V LCDCPEN 1 VLCDx 1011 2 0 V to 3 6 V 3 14 V LCDCPEN 1 VLCDx 1100 2 0 V to 3 6 V 3 20 V LCDCPEN 1 VLCDx 1101 2 2 V to 3 6...

Page 64: ...otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT For specified performance of ADC12 linearity parameters using an external reference voltage or 0 45 4 8 5 0 AVCC as reference 1 fADC12CLK...

Page 65: ...arameters Using the Internal Reference Voltage over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS 1 VCC MIN TYP MAX UNIT ADC1...

Page 66: ...ADC12ON 1 INCH 0Bh tVMID sample 2 2 V 3 V 1000 ns channel 11 is selected 5 Error of conversion result 1 LSB 1 The temperature sensor is provided by the REF module See the REF module parametric IREF re...

Page 67: ...charge and discharge the capacitance array The input capacitance Ci is also the dynamic load for an external reference during conversion The dynamic impedance of the reference supply should follow th...

Page 68: ...max REFVSEL 0 1 or 2 75 REFOUT 0 REFON 0 1 Settling time of reference tSETTLE s AVCC AVCC min AVCC max voltage 6 CVREF CVREF max 75 REFVSEL 0 1 or 2 REFOUT 1 REFON 0 1 1 The reference is supplied to...

Page 69: ...FSET Input offset voltage CBPWRMD 01 10 10 mV CIN Input capacitance 5 pF ON switch closed 3 4 k RSIN Series input resistance OFF switch opened 30 M CBPWRMD 00 CBF 0 450 ns tPD Propagation delay respon...

Page 70: ...ode fMCLK MGR 0 1 MHz FCTL4 MGR0 1 or FCTL4 MGR1 1 1 The cumulative program time must not be exceeded when writing to a 128 byte flash block This parameter applies to all programming methods individua...

Page 71: ...l bandwidth and spacing Also see design note DN005 CC11xx Sensitivity versus Frequency Offset and Crystal Accuracy SWRA122 RF Crystal Oscillator XT2 TA 25 C VCC 3 V unless otherwise noted 1 PARAMETER...

Page 72: ...e RX current 17 sensitivity limit Input at 100 dBm close to 18 5 sensitivity limit 250 Input at 40 dBm well above 17 sensitivity limit Input at 100 dBm close to 16 sensitivity limit 1 2 Input at 40 dB...

Page 73: ...K 250 kBaud GFSK 38 4 kBaud GFSK 500 kBaud MSK ECCN 5E002 TSPA Technology Software Publicly Available CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137 CC430F5135 CC430F5133 www ti com...

Page 74: ...t consumption TX 0xC0 max 36 mA 0xC3 10 33 mA 868 0x8D 0 18 mA 0x2D 6 18 mA 0xC0 max 35 mA 0xC3 10 32 mA 915 0x8D 0 18 mA 0x2D 6 18 mA 1 All measurement results are obtained using the EM430F6137RF900...

Page 75: ...2 0 V 3 0 V 3 6 V PATABLE PARAMETER Power UNIT Setting TA 40 C 25 C 85 C 40 C 25 C 85 C 40 C 25 C 85 C dBm 0xC0 max 36 7 35 2 34 2 38 5 35 5 34 9 37 1 35 7 34 7 Current 0xC3 10 34 0 32 8 32 0 34 2 33...

Page 76: ...MDMCFG2 DEM_DCFILT_OFF 1 The typical current consumption is then reduced by about 2mA close to the sensitivity limit The sensitivity is typically reduced to 109dBm 3 Sensitivity can be traded for cur...

Page 77: ...l filter bandwidth unless otherwise noted Receiver sensitivity 7 90 dBm 2 GFSK modulation by setting MDMCFG2 MOD_FORMAT 2 90 Gaussian filter with BT 0 5 Saturation FIFOTHR CLOSE_IN_RX 0 3 19 dBm Adjac...

Page 78: ...7 CC430F6126 CC430F6125 CC430F5137 CC430F5135 CC430F5133 SLAS554H MAY 2009 REVISED SEPTEMBER 2013 www ti com NOTE 868 3 MHz 2 FSK 5 2 kHz deviation IF frequency is 152 3 kHz digital channel filter ban...

Page 79: ...C430F6126 CC430F6125 CC430F5137 CC430F5135 CC430F5133 www ti com SLAS554H MAY 2009 REVISED SEPTEMBER 2013 NOTE 868 MHz 2 FSK IF frequency is 304 kHz digital channel filter bandwidth is 540 kHz Figure...

Page 80: ...4 101 104 104 101 104 103 101 dBm 433MHz 250 93 94 91 93 93 90 93 93 90 Typical Sensitivity 868 MHz Sensitivity Optimized Setting VCC 2 0 V 3 0 V 3 6 V PARAMETER DATA RATE kBaud UNIT TA 40 C 25 C 85 C...

Page 81: ...elow 1 GHz 46 not included 8 Frequencies above 1 GHz 59 868 10 dBm CW Frequencies within 47 to 74 87 5 to 56 118 174 to 230 470 to 862 MHz Frequencies below 960 MHz 49 915 11 dBm CW Frequencies above...

Page 82: ...ved on the RF output ports Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands TA 25 C VCC 3 V unless otherwise noted 1 PATABLE Setting Output Power dBm 315 MHz 433 MHz 868 MH...

Page 83: ...ical Output Power 868 MHz 1 VCC 2 0 V 3 0 V 3 6 V PARAMETER PATABLE Setting UNIT TA 40 C 25 C 85 C 40 C 25 C 85 C 40 C 25 C 85 C 0xC0 max 11 9 11 2 10 5 11 9 11 2 10 5 11 9 11 2 10 5 0xC3 10 dBm 10 8...

Page 84: ...nd hop time 4 Crystal oscillator running 85 1 88 4 88 4 s PLL RX to TX settling time 5 9 3 9 6 9 6 s PLL TX to RX settling time 6 20 7 21 5 21 5 s PLL calibration time 7 694 721 721 s 1 All measuremen...

Page 85: ...SEPTEMBER 2013 Typical RSSI_offset Values TA 25 C VCC 3 V unless otherwise noted 1 RSSI_OFFSET dB DATA RATE kBaud 433 MHz 868 MHz 1 2 74 74 38 4 74 74 250 74 74 500 74 74 1 All measurement results are...

Page 86: ...57 25 56 26 55 27 54 28 53 33 16 34 15 35 14 36 13 37 12 38 11 45 4 46 3 47 2 48 1 39 10 40 9 41 8 42 7 43 6 44 5 ECCN 5E002 TSPA Technology Software Publicly Available CC430F6137 CC430F6135 CC430F612...

Page 87: ...xx May be added close to the respective pins to reduce emissions at 5GHz to levels required by ETSI ECCN 5E002 TSPA Technology Software Publicly Available CC430F6137 CC430F6135 CC430F6127 CC430F6126 C...

Page 88: ...k RST pullup L1 2 Capacitors 220 pF 0 016 H 0 012 H L3 4 0 033 H 0 027 H 0 018 H L5 0 033 H 0 047 H 0 015 H L6 dnp 2 dnp 2 0 0022 H L7 0 033 H 0 051 H 0 015 H C23 dnp 2 2 7 pF 1 pF C24 220 pF 220 pF...

Page 89: ...MAP_ANALOG Bus Keeper n a CC430F513x ECCN 5E002 TSPA Technology Software Publicly Available CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137 CC430F5135 CC430F5133 www ti com SLAS554H...

Page 90: ...430F513x X X X 1 P1 2 P1MAP2 S20 2 P1 2 I O I 0 O 1 0 X 0 Mapped secondary digital function see Table 9 0 1 3 1 30 3 0 Output driver and input Schmitt trigger disabled X 1 31 0 S22 not available on CC...

Page 91: ...P1 5 to P1 7 Pin Functions CONTROL BITS SIGNALS 1 PIN NAME P1 x x FUNCTION P1DIR x P1SEL x P1MAPx P1 5 P1MAP5 R23 5 P1 5 I O I 0 O 1 0 X Mapped secondary digital function see Table 9 0 1 2 1 30 2 R23...

Page 92: ...mparator_B Pad Logic To ADC12 INCHx x n a CC430F612x CBPD x P2REN x P2MAP x PMAP_ANALOG Bus Keeper ECCN 5E002 TSPA Technology Software Publicly Available CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC...

Page 93: ...Bus Keeper to from Reference n a CC430F612x Direction 0 Input 1 Output CBPD x P2REN x P2MAP x PMAP_ANALOG ECCN 5E002 TSPA Technology Software Publicly Available CC430F6137 CC430F6135 CC430F6127 CC430...

Page 94: ...30F513x CBPD x P2REN x P2MAP x PMAP_ANALOG Bus Keeper ECCN 5E002 TSPA Technology Software Publicly Available CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137 CC430F5135 CC430F5133 SLA...

Page 95: ...1 X CB4 4 X X X 1 P2 5 P2MAP5 CB5 5 P2 5 I O I 0 O 1 0 X 0 A5 VREF VeREF Mapped secondary digital function see Table 9 0 1 2 1 30 2 0 A5 VREF VeREF not available on CC430F612x 3 X 1 31 X CB5 4 X X X 1...

Page 96: ...PMAP_ANALOG Bus Keeper n a CC430F513x ECCN 5E002 TSPA Technology Software Publicly Available CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137 CC430F5135 CC430F5133 SLAS554H MAY 2009 R...

Page 97: ...le 9 0 1 3 1 30 3 0 Output driver and input Schmitt trigger disabled X 1 31 0 S13 not available on CC430F513x X X X 1 P3 4 P3MAP4 S14 4 P3 4 I O I 0 O 1 0 X 0 Mapped secondary digital function see Tab...

Page 98: ...Technology Software Publicly Available CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137 CC430F5135 CC430F5133 SLAS554H MAY 2009 REVISED SEPTEMBER 2013 www ti com Port P4 P4 0 to P4 7...

Page 99: ...N A 0 1 0 DVSS 1 1 0 S3 X X 1 P4 2 P4MAP7 S4 2 P4 2 I O I 0 O 1 0 0 N A 0 1 0 DVSS 1 1 0 S4 X X 1 P4 3 P4MAP3 S5 3 P4 3 I O I 0 O 1 0 0 N A 0 1 0 DVSS 1 1 0 S5 X X 1 P4 4 P4MAP4 S6 4 P4 4 I O I 0 O 1...

Page 100: ...ublicly Available CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137 CC430F5135 CC430F5133 SLAS554H MAY 2009 REVISED SEPTEMBER 2013 www ti com Port P5 P5 0 Input Output With Schmitt Tri...

Page 101: ...ON P5DIR x P5SEL 0 P5SEL 1 XT1BYPASS P5 0 XIN 0 P5 0 I O I 0 O 1 0 X X XIN crystal mode 2 X 1 X 0 XIN bypass mode 2 X 1 X 1 P5 1 XOUT 1 P5 1 I O I 0 O 1 0 X X XOUT crystal mode 3 X 1 X 0 P5 1 I O 3 X...

Page 102: ...ly Table 55 Port P5 P5 2 to P5 3 Pin Functions CC430F613x and CC430F612x only CONTROL BITS SIGNALS 1 PIN NAME P5 x x FUNCTION P5DIR x P5SEL x LCDS0 1 P5 2 S0 2 P5 2 I O I 0 O 1 0 0 N A 0 1 0 DVSS 1 1...

Page 103: ...Schmitt Trigger CC430F613x and CC430F612x only Table 57 Port P5 P5 5 to P5 7 Pin Functions CC430F613x and CC430F612x only CONTROL BITS SIGNALS 1 PIN NAME P5 x x FUNCTION P5DIR x P5SEL x LCDS24 26 P5 5...

Page 104: ...gy Software Publicly Available CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137 CC430F5135 CC430F5133 SLAS554H MAY 2009 REVISED SEPTEMBER 2013 www ti com Port J J 0 JTAG pin TDO Input...

Page 105: ...1 TDO 3 X PJ 1 TDI TCLK 1 PJ 1 I O 2 I 0 O 1 TDI TCLK 3 4 X PJ 2 TMS 2 PJ 2 I O 2 I 0 O 1 TMS 3 4 X PJ 3 TCK 3 PJ 3 I O 2 I 0 O 1 TCK 3 4 X 1 X don t care 2 Default condition 3 The pin direction is c...

Page 106: ...nit per unit per unit Die X position 01A0Eh 2 per unit per unit per unit per unit per unit Die Y position 01A10h 2 per unit per unit per unit per unit per unit Test results 01A12h 2 per unit per unit...

Page 107: ...01A04h 1 61h 61h 61h Device ID 01A05h 1 27h 26h 25h Hardware revision 01A06h 1 per unit per unit per unit Firmware revision 01A07h 1 per unit per unit per unit Die Record Die Record Tag 01A08h 1 08h...

Page 108: ...n and Firmware revision in Device Descriptor Tables with per unit Table 3 Corrected USCI signal names for pins 5 and 6 descriptions unchanged 12 Bit ADC Linearity Parameters Using an External Referenc...

Page 109: ...U NIPDAU Level 3 260C 168 HR 40 to 85 CC430 F5137 CC430F5137IRGZR ACTIVE VQFN RGZ 48 2500 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 85 CC430 F5137 CC430F5137IRGZT ACTIVE VQFN RGZ 48 250...

Page 110: ...EDEC industry standard classifications and peak solder temperature 4 There may be additional marking which relates to the logo the lot trace code information or the environmental category on the devic...

Page 111: ...12 0 16 0 Q2 CC430F6126IRGCT VQFN RGC 64 250 180 0 16 4 9 3 9 3 1 5 12 0 16 0 Q2 CC430F6127IRGCR VQFN RGC 64 2000 330 0 16 4 9 3 9 3 1 5 12 0 16 0 Q2 CC430F6127IRGCT VQFN RGC 64 250 180 0 16 4 9 3 9...

Page 112: ...36 6 336 6 28 6 CC430F6126IRGCT VQFN RGC 64 250 213 0 191 0 55 0 CC430F6127IRGCR VQFN RGC 64 2000 336 6 336 6 28 6 CC430F6127IRGCT VQFN RGC 64 250 213 0 191 0 55 0 CC430F6135IRGCR VQFN RGC 64 2000 336...

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Page 119: ...duct s identified in such TI Resource NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY...

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