ECCN 5E002 TSPA - Technology / Software Publicly Available
CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125
CC430F5137, CC430F5135, CC430F5133
SLAS554H – MAY 2009 – REVISED SEPTEMBER 2013
www.ti.com
TA0
TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 can support multiple
capture/compares, PWM outputs, and interval timing. TA0 also has extensive interrupt capabilities. Interrupts
may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 13. TA0 Signal Connections
MODULE OUTPUT
DEVICE OUTPUT
DEVICE INPUT SIGNAL
MODULE INPUT NAME
MODULE BLOCK
SIGNAL
SIGNAL
PM_TA0CLK
TACLK
ACLK (internal)
ACLK
Timer
NA
SMCLK (internal)
SMCLK
RFCLK/192
(1)
INCLK
PM_TA0CCR0A
CCI0A
PM_TA0CCR0A
DV
SS
CCI0B
CCR0
TA0
DV
SS
GND
DV
CC
V
CC
PM_TA0CCR1A
CCI1A
PM_TA0CCR1A
ADC12 (internal)
(2)
CBOUT (internal)
CCI1B
ADC12SHSx = {1}
CCR1
TA1
DV
SS
GND
DV
CC
V
CC
PM_TA0CCR2A
CCI2A
PM_TA0CCR2A
ACLK (internal)
CCI2B
CCR2
TA2
DV
SS
GND
DV
CC
V
CC
PM_TA0CCR3A
CCI3A
PM_TA0CCR3A
GDO1 from Radio
CCI3B
(internal)
CCR3
TA3
DV
SS
GND
DV
CC
V
CC
PM_TA0CCR4A
CCI4A
PM_TA0CCR4A
GDO2 from Radio
CCI4B
(internal)
CCR4
TA4
DV
SS
GND
DV
CC
V
CC
(1)
If a different RFCLK divider setting is selected for a radio GDO output, this divider setting is also used for the Timer_A INCLK.
(2)
Only on CC430F613x and CC430F513x
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CC430F6137 CC430F6135 CC430F6127 CC430F6126 CC430F6125 CC430F5137
CC430F5135 CC430F5133
