SWRS046H – NOVEMBER 2006 – REVISED MARCH 2015
Table 5-18. MAIN Register (00h) When Using Automatic Power-up Sequencing
(RXTX = 0, PD_MODE[1:0] =11) (continued)
DEFAULT
REGISTER
NAME
ACTIVE
DESCRIPTION
VALUE
MAIN[3:2]
SEQ_CAL[1:0]
—
—
Controls PLL calibration before re-entering power down
0: Never perform PLL calibration as part of sequence
1: Always perform PLL calibration at end of sequence
2: Perform PLL calibration at end of every 16th sequence
3: Perform PLL calibration at end of every 256th sequence
MAIN[1]
SEQ_PD
—
↑
↑
1: Put the chip in power down and wait for start of new power-up
sequence
MAIN[0]
RESET_N
—
L
Reset, active low. Writing RESET_N low will write default values to all
other registers than MAIN. Bits in MAIN do not have a default value
and will be written directly through the configuration interface. Must be
set high to complete reset.
Table 5-19. INTERFACE Register (01h)
(1)
DEFAULT
REGISTER
NAME
ACTIVE
DESCRIPTION
VALUE
INTERFACE[7]
XOSC_BYPASS
0
H
Bypass internal crystal oscillator, use external clock
0: Internal crystal oscillator is used, or external sine wave fed
through a coupling capacitor
1: Internal crystal oscillator in power down, external clock with rail-
to-rail swing is used
INTERFACE[6]
SEP_DI_DO
0
H
Use separate pin for RX data output
0: DIO is data output in RX and data input in TX. LOCK pin is
available (Normal operation).
1: DIO is always input, and a separate pin is used for RX data
output (synchronous mode: LOCK pin, asynchronous mode: DCLK
pin).
If SEP_DI_DO=1 and SEQ_PSEL=0 in SEQUENCING register then
negative transitions on DIO is used to start power-up sequencing when
PD_MODE=3 (power-up sequencing is enabled).
INTERFACE[5]
DCLK_LOCK
0
H
Gate DCLK signal with PLL lock signal in synchronous mode
Only applies when PD_MODE = "01"
0: DCLK is always 1
1: DCLK is always 1 unless PLL is in lock
INTERFACE[4]
DCLK_CS
0
H
Gate DCLK signal with carrier sense indicator in synchronous mode
Use when receive chain is active (in power up)
Always set to 0 in TX mode.
0: DCLK is independent of carrier sense indicator.
1: DCLK is always 1 unless carrier sense is indicated
INTERFACE[3]
EXT_PA
0
H
Use PA_EN pin to control external PA
0: PA_EN pin always equals EXT_PA_POL bit
1: PA_EN pin is asserted when internal PA is turned on
INTERFACE[2]
EXT_LNA
0
H
Use LNA_EN pin to control external LNA
0: LNA_EN pin always equals EXT_LNA_POL bit
1: LNA_EN pin is asserted when internal LNA is turned on
INTERFACE[1]
EXT_PA_POL
0
H
Polarity of external PA control
0: PA_EN pin is "0" when activating external PA
1: PA_EN pin is “1” when activating external PA
INTERFACE[0]
EXT_LNA_POL
0
H
Polarity of external LNA control
0: LNA_EN pin is “0” when activating external LNA
1: LNA_EN pin is “1” when activating external LNA
(1)
If TF_ENABLE=1 or TA_ENABLE=1 in TEST4 register, then INTERFACE[3:0] controls analog test module: INTERFACE[3] = TEST_PD,
INTERFACE[2:0] = TEST_MODE[2:0]. Otherwise, TEST_PD=1 and TEST_MODE[2:0]=001.
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Detailed Description
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