Texas Instruments CC1020, Manual

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CC1020
www.ti.com SWRS046H – NOVEMBER 2006 – REVISED MARCH 2015
5.9.11 Carrier Sense
The carrier sense signal is based on the RSSI value and a programmable threshold. The carrier sense
function can be used to simplify the implementation of a CSMA (Carrier Sense Multiple Access) medium
access protocol.
Carrier sense threshold level is programmed by CS_LEVEL[4:0] in the VGA4 register and
VGA_SETTING[4:0] in the VGA3 register.
VGA_SETTING[4:0] sets the maximum gain in the VGA. This value must be set so that the ADC works
with optimum dynamic range for a certain channel filter bandwidth. The detected signal strength (after the
ADC) will therefore depend on this setting.
CS_LEVEL[4:0] sets the threshold for this specific VGA_SETTING[4:0] value. If the VGA_SETTING[4:0] is
changed, the CS_LEVEL[4:0] must be changed accordingly to maintain the same absolute carrier sense
threshold. See
Figure 5-15 for an explanation of the relationship between RSSI, AGC and carrier sense
settings.
The carrier sense signal can be read as the CARRIER_SENSE bit in the STATUS register.
The carrier sense signal can also be made available at the LOCK pin by setting LOCK_SELECT[3:0] =
0100 in the LOCK register.
5.9.12 Automatic Power-up Sequencing
CC1020 has a built-in automatic power-up sequencing state machine. By setting the CC1020 into this
mode, the receiver can be powered-up automatically by a wake-up signal and will then check for a carrier
signal (carrier sense). If carrier sense is not detected, it returns to power-down mode. A flow chart for
automatic power-up sequencing is shown in
Figure 5-16 .
The automatic power-up sequencing mode is selected when PD_MODE[1:0] = 11 in the MAIN register.
When the automatic power-up sequencing mode is selected, the functionality of the MAIN register is
changed and used to control the sequencing.
By setting SEQ_PD = 1 in the MAIN register, CC1020 is set in power down mode. If SEQ_PSEL = 1 in the
SEQUENCING register the automatic power-up sequence is initiated by a negative transition on the PSEL
pin.
If SEQ_PSEL = 0 in the SEQUENCING register, then the automatic power-up sequence is initiated by a
negative transition on the DIO pin (as long as SEP_DI_DO = 1 in the INTERFACE register).
Sequence timing is controlled through RX_WAIT[2:0] AND CS_WAIT[3:0] in the SEQUENCING register.
VCO and PLL calibration can also be done automatically as a part of the sequence. This is controlled
through SEQ_CAL[1:0] in the MAIN register. Calibration can be done every time, every 16th sequence,
every 256th sequence, or never. See
Section 5.22.1 description for details. A description of when to do,
and how the VCO and PLL self-calibration is done, is given in Section 5.12.2 .
See also Application Note AN070 CC1020 Automatic Power-Up Sequencing ( SWRA279 ).
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