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SBAS367F
–
JUNE 2007
–
REVISED FEBRUARY 2011
Table 1. ADS1274/ADS1278 PIN DESCRIPTIONS (continued)
PIN
NAME
NO.
FUNCTION
DESCRIPTION
AINN1
4
Analog input
AINN2
2
Analog input
AINN3
64
Analog input
ADS1278:
AINN[8:1] Negative analog input, channels 8 through 1.
AINN4
62
Analog input
AINN5
52
Analog input
ADS1274:
AINN[8:5] Connected to internal ESD rails. The inputs may float.
AINN[4:1] Negative analog input, channels 4 through 1.
AINN6
50
Analog input
AINN7
48
Analog input
AINN8
46
Analog input
AVDD
5, 44, 53, 60
Analog power supply
Analog power supply (4.75V to 5.25V).
VCOM
55
Analog output
AVDD/2 Unbuffered voltage output.
VREFN
57
Analog input
Negative reference input.
VREFP
56
Analog input
Positive reference input.
CLK
27
Digital input
Master clock input (f
CLK
).
CLK input divider control:
1 = 37MHz (High-Speed mode)/otherwise 27MHz
CLKDIV
10
Digital input
0 = 13.5MHz (low-power)/5.4MHz (low-speed)
DGND
7, 21, 24, 25
Digital ground
Digital ground power supply.
DIN
12
Digital input
Daisy-chain data input.
DOUT1
20
Digital output
DOUT1 is TDM data output (TDM mode).
DOUT2
19
Digital output
DOUT3
18
Digital output
ADS1278:
DOUT[8:1] Data output for channels 8 through 1.
DOUT4
17
Digital output
DOUT5
16
Digital output
ADS1274:
DOUT[8:5] Internally connected to active circuitry; outputs are
driven.
DOUT6
15
Digital output
DOUT[4:1] Data output for channels 4 through 1.
DOUT7
14
Digital output
DOUT8
13
Digital output
DRDY/
29
Digital input/output
Frame-Sync protocol: frame clock input; SPI protocol: data ready output.
FSYNC
DVDD
26
Digital power supply
Digital core power supply.
FORMAT0
32
Digital input
FORMAT[2:0] Selects Frame-Sync/SPI protocol, TDM/discrete data outputs,
FORMAT1
31
Digital input
fixed/dynamic position TDM data, and modulator mode/normal operating mode.
FORMAT2
30
Digital input
IOVDD
22, 23
Digital power supply
I/O power supply (+1.65V to +3.6V).
MODE0
34
Digital input
MODE[1:0] Selects High-Speed, High-Resolution, Low-Power, or Low-Speed
mode operation.
MODE1
33
Digital input
PWDN1
42
Digital input
PWDN2
41
Digital input
PWDN3
40
Digital input
ADS1278:
PWDN[8:1] Power-down control for channels 8 through 1.
PWDN4
39
Digital input
PWDN5
38
Digital input
ADS1274:
PWDN[8:5] must = 0V.
PWDN[4:1] Power-down control for channels 4 through 1.
PWDN6
37
Digital input
PWDN7
36
Digital input
PWDN8
35
Digital input
SCLK
28
Digital input/output
Serial clock input, Modulator clock output.
SYNC
11
Digital input
Synchronize input (all channels).
TEST0
8
Digital input
TEST[1:0] Test mode select:
01 = Do not use
00 = Normal operation
10 = Do not use
11 = Test mode
TEST1
9
Digital input
©
2007
–
2011, Texas Instruments Incorporated
7
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