SCLK
FSYNC
DOUT
DIN
t
DOHD
t
FPW
t
SCLK
t
SF
t
SPW
t
SPW
t
FRAME
t
FPW
t
FS
t
DIHD
t
MSBPD
t
DIST
Bit 23 (MSB)
Bit 22
Bit 21
t
DOPD
CLK
t
CPW
t
CPW
t
CS
t
CLK
SBAS367F
–
JUNE 2007
–
REVISED FEBRUARY 2011
FRAME-SYNC FORMAT TIMING
FRAME-SYNC FORMAT TIMING SPECIFICATION
For T
A
=
–
40
°
C to +105
°
C, IOVDD = 1.65V to 3.6V, and DVDD = 1.65V to 2.2V, unless otherwise noted.
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
High-Speed mode
27
10,000
ns
t
CLK
CLK period (1/f
CLK
) (see
Other modes
37
10,000
ns
t
CPW
CLK positive or negative pulse width
11
ns
t
CS
Falling edge of CLK to falling edge of SCLK
–
0.25
0.25
t
CLK
t
FRAME
Frame period (1/f
DATA
)
(1)
256
2560
t
CLK
t
FPW
FSYNC positive or negative pulse width
1
t
SCLK
t
FS
Rising edge of FSYNC to rising edge of SCLK
5
ns
t
SF
Rising edge of SCLK to rising edge of FSYNC
5
ns
t
SCLK
SCLK period
(2)
1
t
CLK
t
SPW
SCLK positive or negative pulse width
0.4
t
CLK
t
DOHD
(3) (4)
SCLK falling edge to old DOUT invalid (hold time)
10
ns
31
ns
t
DOPD
(4)
SCLK falling edge to new DOUT valid (propagation delay)
21
ns
(5)
25
ns
(6)
31
ns
t
MSBPD
FSYNC rising edge to DOUT MSB valid (propagation delay)
21
ns
(5)
25
ns
(6)
t
DIST
New DIN valid to falling edge of SCLK (setup time)
6
ns
t
DIHD
(3)
Old DIN valid to falling edge of SCLK (hold time)
6
ns
(1)
Depends on MODE[1:0] and CLKDIV selection. See
(f
CLK
/f
DATA
).
(2)
SCLK must be continuously running and limited to ratios of 1, 1/2, 1/4, and 1/8 of f
CLK
.
(3)
t
DOHD
(DOUT hold time) and t
DIHD
(DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and
ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is
>
4ns.
(4)
Load on DOUT = 20pF.
(5)
DOUT1, TDM mode, IOVDD = 3.15V to 3.45V, and DVDD = 2V to 2.2V.
(6)
DOUT1, TDM mode, IOVDD = 3.15V to 3.45V, and DVDD = 1.7V to 1.9V.
©
2007
–
2011, Texas Instruments Incorporated
9
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