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SLAU776 – May 2018
Copyright © 2018, Texas Instruments Incorporated
Optional ADC12DL3200EVM Configurations
Appendix B
SLAU776 – May 2018
Optional ADC12DL3200EVM Configurations
This appendix provides settings for optional ADC device configuration in HSDC Pro.
B.1
Modifying the EVM for Optional Clocking Support
The LMK04828 provides a buffered copy of the onboard 100-MHz VCXO to the LMX2582. When the
optional 10-MHz reference clock is connected, the 100-MHz VCXO output is frequency locked to the 10-
MHz reference. This process enables coherent sampling of the analog input signal. The EVM can be
configured to use an external ADC clock with the following steps (see
1. Modify the hardware:
a. Remove C114 and C124, populate C24 and C25.
2. Connect the signal generators:
a. Connect the 10-MHz reference from Sig Gen 1 to Sig Gen 2.
b. Configure Sig Gen 2 to use the 10-MHz reference input from Sig Gen 1.
c. Sig Gen 1 connects to DEVCLK (J12). Set to the generator frequency to the desired F
CLK
. Set
output level to +9 dBm.
d. Sig Gen 2 connects to the desired analog input with output level at 0 dBm for the starting point.
3. Program the GUI:
a. In the
EVM
tab, set the clock source to
External
.
b. Enter the
Sampling Frequency
(F
CLK
) in step 2b.
Figure B-1. External CLK Configuration
The ADC12DL3200EVM includes a reference clock input (CLKIN0) that allows the user to sync the
LMK04828 to an external 10-MHz reference allowing for coherent sampling
The LMX2582 and LMK04828 may be reconfigured to exercise more features, but this EVM is not
intended to be a full evaluation platform for these devices. For a full evaluation platform, see the
and
.
