Texas Instruments ADC DJ 00RF Series, User Manual

Page: 18 / 32

7.2.1 External Clocking Option (Default)
By default, the EVM is configured to use the external clock option. The user provide and external clock signal for
both the ADC sampling clock(DEVCLK at J10) and also the Reference clock(REF CLK at J17) which feed into
the LMK04828 and is used in clock distribution mode and provides the FPGA reference clock, FPGA SYSREF
signal and ADC SYSREF signal. If coherent sampling is desired the external clocking has to be used.
Figure 7-1
shows the block diagram of external clocking option:
The EVM can be configured to use external clocks with the following steps (see Figure 7-4 ):
1. Modify the hardware:
a. Remove R171 and R174, populate C2 and C3.
b. Remove C52 and C306, populate C60 and C61
c. Install Jumper J13
SYNC
SYSREFREQ
OSCIN RFOUTA
RFOUTB
SDCLKx
SDCLKx
DCLKx
SDCLKx
DA[15:0]
SYNC
FPGA_CLK[3:0]
FPGA_SYSREF
CLKIN0
CLKIN1
LMK61E2
LMK00304
SDCLKx
LMK04828
LMX2594
ADC12DJ5200RF
CLK
SYSREF
DA[15:0]
FMC
SYNC
REFCLK
(J17)
260 MHz
SYSREF
32.5 MHz
Board SYNC
External Clock
/N
SYSR
EF
3
2
.5
MH
z
REFCLK
(J10)
5200 MHz
Figure 7-1. ADC12DJ5200RFEVM Clocking System Block Diagram
HSDC Pro Settings for Optional ADC Device Configuration www.ti.com
18 ADCxxDJxx00RF Evaluation Module SLAU640A – APRIL 2019 – REVISED JUNE 2021
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated