TPMC671 User Manual Issue 1.1
Page 16 of 28
4.2.7 Falling Edge Interrupt Status Register
The Falling Edge Interrupt Status Register is a word wide read/write register.
Bit
Symbol
Description
Access
Reset
Value
15 INT_STA_L16
14 INT_STA_L15
13 INT_STA_L14
12 INT_STA_L13
11 INT_STA_L12
10 INT_STA_L11
9 INT_STA_L10
8 INT_STA_L9
7 INT_STA_L8
6 INT_STA_L7
5 INT_STA_L6
4 INT_STA_L5
3 INT_STA_L4
2 INT_STA_L3
1 INT_STA_L2
0 INT_STA_L1
Read access:
0 = no interrupt request pending
1 = interrupt request pending
Write access:
0 = no effect
1 = clear pending interrupt request
Bit 0 of this register reflects the interrupt request state
of input line 1 for the falling edge, bit 15 reflects the
interrupt request state of input line 16 for the falling
edge.
An interrupt request for a specific input line is cleared
by writing ‘1’ to the according bit of the Falling Edge
Interrupt Status Register.
R/W
0x0000
Figure 4-9 : Falling Edge Interrupt Status Register
