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Tews Technologies TPMC671, User Manual

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Tews Technologies TPMC671 User Manual Download Page 22

 

 

TPMC671 User Manual Issue 1.1 

Page 22 of 28 

5.3  Configuration EEPROM 

After power-on or PCI reset, the PCI9030 loads initial configuration register data from the on board 
configuration EEPROM. 

The configuration EEPROM contains the following configuration data: 

•

  Address 0x00 to 0x27 : PCI9030 PCI Configuration Register Values 

•

  Address 0x28 to 0x87 : PCI9030 Local Configuration Register Values 

•

  Address 0x88 to 0xFF : Reserved 

See the PCI9030 Manual for more information. 

Address 

Offset 

 

0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E 

0x00  0x029F 0x1498 0x0280 0x0000 0x1180 0x0000  s.b. 0x1498 

0x10  0x0000 0x0040 0x0000 0x0100 0x4801 0x0001 0x0000 0x0000 

0x20  0x0000 0x0006 0x0000 0x0003 0x0FFF 0xFFF1 0x0000 0x0000 

0x30  0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0001 

0x40  0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 

0x50 0x0171 

0x78A0 

0x0000 

0x0000 0x0000 0x0000 0x0000 0x0000 

0x60  0x0000 0x0000 0x0000 0x0009 0x0000 0x0000 0x0000 0x0000 

0x70  0x0000 0x0000 0x0030 0x0041 0x0078 0x0000 0x0249 0x2492 

0x80  0x0000 0x0000 0x0000 0x0000 0xFFFF 0xFFFF 0xFFFF 0xFFFF 

0x90  0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 

0xA0  0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 

0xB0  0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 

0xC0  0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 

0xD0  0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 

0xE0  0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 

0xF0  0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 

Figure 5-4 :  Configuration EEPROM TPMC671-xx 

Subsystem-ID Value (Offset 0x0C):  

TPMC671-10:  0x000A 

TPMC671-11: 0x000B 

TPMC671-20: 0x0014 

TPMC671-21: 0x0015 

Summary of Contents for TPMC671

Page 1: ...e 1 1 October 2004 TEWS TECHNOLOGIES GmbH Am Bahnhof 7 25469 Halstenbek Germany Phone 49 0 4101 4058 0 Fax 49 0 4101 4058 19 e mail info tews com www tews com TEWS TECHNOLOGIES LLC 1 E Liberty Street...

Page 2: ...e that this manual is accurate and complete However TEWS TECHNOLOGIES GmbH reserves the right to change the product described in this document at any time without notice TEWS TECHNOLOGIES GmbH is not...

Page 3: ...4 Rising Edge Interrupt Enable Register 13 4 2 5 Falling Edge Interrupt Enable Register 14 4 2 6 Rising Edge Interrupt Status Register 15 4 2 7 Falling Edge Interrupt Status Register 16 4 2 8 Debounc...

Page 4: ...E 4 8 RISING EDGE INTERRUPT STATUS REGISTER 15 FIGURE 4 9 FALLING EDGE INTERRUPT STATUS REGISTER 16 FIGURE 4 10 DEBOUNCE TIME REGISTER 17 FIGURE 4 11 FORMULAS TO DETERMINE PRELOAD VALUE 17 FIGURE 4 12...

Page 5: ...ounce time All inputs can generate an interrupt The signal edge handling is programmable to interrupt on rising falling or both edges of the input signal The TPMC671 has 16 digital high side or low si...

Page 6: ...or both edges Outputs TPMC671 10 20 TPMC671 11 21 16 digital high side switch Outputs 16 digital low side switch Outputs Output Isolation Optocouplers for galvanic isolation also isolated to each othe...

Page 7: ...UT 13 OUT 14 OUT 15 OUT 16 Figure 3 1 Isolated Digital Outputs 3 1 2 Output Polarity Each output can be individually switched to the according power supply VS_Ox high side switch or GND_Ox low side sw...

Page 8: ...these inputs is 24V DC The switching level of the inputs is between 7 5V and 14V All inputs are isolated by optocouplers from the computer system and are also isolated against each other 3 2 2 Debounc...

Page 9: ...0x1C Not Used 2 4 0x20 Not Used 3 5 0x24 Not Used Figure 4 1 PCI9030 Local Space Configuration 4 2 Local Register Space Address Map PCI Base Address PCI9030 PCI Base Address 2 Offset 0x18 in PCI Confi...

Page 10: ...12 OUTPUT13 11 OUTPUT12 10 OUTPUT11 9 OUTPUT10 8 OUTPUT9 7 OUTPUT8 6 OUTPUT7 5 OUTPUT6 4 OUTPUT5 3 OUTPUT4 2 OUTPUT3 1 OUTPUT2 0 OUTPUT1 To set an output line active write 1 to the corresponding bit F...

Page 11: ...he inputs Bit Symbol Description Access Reset Value 15 INPUT16 14 INPUT15 13 INPUT14 12 INPUT13 11 INPUT12 10 INPUT11 9 INPUT10 8 INPUT9 7 INPUT8 6 INPUT7 5 INPUT6 4 INPUT5 3 INPUT4 2 INPUT3 1 INPUT2...

Page 12: ...debounce function for all 16 inputs 0 disables debounce function R W 0 1 WD_ENA Watchdog Enable 1 enables watchdog for all 16 outputs 0 disables watchdog function R W 0 0 INT_ENA Global Interrupt Ena...

Page 13: ...H12 10 INT_ENA_H11 9 INT_ENA_H10 8 INT_ENA_H9 7 INT_ENA_H8 6 INT_ENA_H7 5 INT_ENA_H6 4 INT_ENA_H5 3 INT_ENA_H4 2 INT_ENA_H3 1 INT_ENA_H2 0 INT_ENA_H1 0 Interrupt for input line disabled 1 Interrupt fo...

Page 14: ...12 10 INT_ENA_L11 9 INT_ENA_L10 8 INT_ENA_L9 7 INT_ENA_L8 6 INT_ENA_L7 5 INT_ENA_L6 4 INT_ENA_L5 3 INT_ENA_L4 2 INT_ENA_L3 1 INT_ENA_L2 0 INT_ENA_L1 0 Interrupt for input line disabled 1 Interrupt for...

Page 15: ...NT_STA_H5 3 INT_STA_H4 2 INT_STA_H3 1 INT_STA_H2 0 INT_STA_H1 Read access 0 no interrupt request pending 1 interrupt request pending Write access 0 no effect 1 clear pending interrupt request Bit 0 of...

Page 16: ...T_STA_L5 3 INT_STA_L4 2 INT_STA_L3 1 INT_STA_L2 0 INT_STA_L1 Read access 0 no interrupt request pending 1 interrupt request pending Write access 0 no effect 1 clear pending interrupt request Bit 0 of...

Page 17: ...fter power on or reset Any debounce time in the range of 7 s to 440ms can be programmed in steps of ca 7 s The debounce time is common for all 16 inputs R W 0x0000 Figure 4 10 Debounce Time Register T...

Page 18: ...58 0x003A 0 500 0 071 73 0x0049 0 600 0 085 88 0x0058 0 700 0 100 103 0x0067 0 800 0 114 118 0x0076 0 900 0 128 132 0x0084 1 000 0 142 147 0x0093 2 000 0 285 296 0x0128 3 000 0 428 445 0x01BD 4 000 0...

Page 19: ...x1C PCI Base Address 3 for Local Address Space 1 Y 00000000 0x20 PCI Base Address 4 for Local Address Space 2 Y 00000000 0x24 PCI Base Address 5 for Local Address Space 3 Y 00000000 0x28 PCI Cardbus I...

Page 20: ...apping starting at bit location 11 the first bit set to 1 determines the required PCI Expansion ROM size For example if bit 5 of a PCI Base Address Register is detected as the first bit set to 1 the P...

Page 21: ...ROM Range 0x0000_0000 0x14 Local Re map Register Space 0 0x0000_0001 0x18 Local Re map Register Space 1 0x0000_0000 0x1C Local Re map Register Space 2 0x0000_0000 0x20 Local Re map Register Space 3 0...

Page 22: ...000 0x0000 0x0000 0x0000 0x0000 0x0001 0x40 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x50 0x0171 0x78A0 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x60 0x0000 0x0000 0x0000 0x0009 0x0000...

Page 23: ...Adapter Software Reset bit is set in the PCI9030 local configuration register CNTRL offset 0x50 CNTRL 30 PCI Adapter Software Reset Value of 1 resets the PCI9030 and issues a reset to the Local Bus L...

Page 24: ...ian PCI Bus Little Endian Byte 0 AD 7 0 Byte 1 AD 15 8 Byte 2 AD 23 16 Byte 3 AD 31 24 Every Local Address Space 0 3 and the Expansion ROM Space can programmed to operate in Big or Little Endian Mode...

Page 25: ...indicates Little Endian For further information please refer to the PCI9030 manual which is also part of the TPMC671 ED Engineering Documentation Use the PCI Base Address 0 Offset or PCI Base Address...

Page 26: ...ge 26 of 28 7 Installation 7 1 Input Wiring Figure 7 1 Input Wiring 7 2 Output Wiring High Side Switch 10 20 Figure 7 2 Output Wiring High Side Switch 7 3 Output Wiring Low Side Switch 11 21 Figure 7...

Page 27: ...ne 14 48 GND_O4 Ground OUT 13 OUT 16 15 OUT 15 Output Line 15 49 IN 1 Ground IN 1 16 OUT 16 Output Line 16 50 IN 2 Ground IN 2 17 IN 1 Input Line 1 51 IN 3 Ground IN 3 18 IN 2 Input Line 2 52 IN 4 Gro...

Page 28: ...S_O1 External Supply OUT1 OUT4 34 VS_O1 External Supply OUT1 OUT4 35 VS_O2 External Supply OUT5 OUT8 36 VS_O2 External Supply OUT5 OUT8 37 VS_O3 External Supply OUT9 OUT12 38 VS_O3 External Supply OUT...

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