TPMC671 User Manual Issue 1.1
Page 8 of 28
3.1.4 Output
Watchdog
Writing ‘1’ into bit 1 of the Global Control Register enables the hardware watchdog function. The
status of the watchdog is indicated at the bit 3 of Global Control Register.
Any software access (read or write) to the Data Output Register of the TPMC671 will retrigger the
watchdog. The maximum time between two accesses is set to 120ms, if the time expires without a
software access all outputs go into the ‘OFF’ state. At the same time the watchdog status will change
from ‘0’ to ‘1’ and lock the Data Output Register. This prevents a write access to the Data Output
Register.
Writing ‘1’ to the watchdog status (Bit 3 Control Register) clears this bit and also unlocks the Output
Register. After unlocking the Data Output Register, the outputs stays in the ‘OFF’ state till the next
write access to this Register.
The watchdog is disabled after power-on or reset.
3.2 Digital Inputs
3.2.1 Optical
Isolation
The TPMC671 has 16 digital inputs. The standard signal level for these inputs is 24V DC. The
switching level of the inputs is between 7.5V and 14V. All inputs are isolated by optocouplers from the
computer system and are also isolated against each other.
3.2.2 Debounce
Function
A programmable debounce function common for all inputs is implemented on the TPMC671. There is
only one debounce time adjustable for all 16 digital inputs.
If the debounce function is enabled, the input pin must be static for the programmed debounce time
before the rising or falling edge is recognized as valid. So only after a correct identification the Data
Input Register is updated and an interrupt is generated.
The debounce function is disabled after power-on and reset. The debounce time is set to value
‘0’ after power-on and reset.
3.2.3 Interrupt
Logic
Interrupt generation can be individually programmed for each channel and input transition. To enable
the interrupt after a reset, the Global Interrupt Enable bit in the Control Register must be set to the
value ‘1’. Also the respective bit for rising or falling edge in the Rising Edge / Falling Edge Interrupt
Enable Registers must be set.
The Global Interrupt Enable and also all individually interrupt enable bits are disabled after
power-on and reset.
