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V104

Appendix F: Software Glossary

F-1

Appendix F:

Software Glossary

The following is a glossary of library functions for the V104.

void ve_init(void)

ve.h

Initializes the V25 processor. The following is the source code for ve_init()

pokeb(0xfff0,0x02,0x80); /* Set PMC0 P07=CLK */

pokeb(0xfff0,0x01,0xd7); /* Set PM0 for input, P05=LED P03=HWD output */

pokeb(0xfff0,0x0a,0x80); /* Set PMC1 P17 for READY */

pokeb(0xfff0,0x09,0xaf); /* Set PM1 for input, P14=RTS1,P16=RTS0 OUTPUT */

pokeb(0xfff0,0x12,0x00); /* Set P20-P27 for port mode */

pokeb(0xfff0,0x11,0xf7);// Set PM2 for input, P23=EN485 output

Reference: led.c

void ve_reset(void)

ve.h

Resets the V25 processor.

void delay_ms(int m)

ve.h

Approximate microsecond delay. Does not use timer.

Var: m – Delay in approximate ms

Reference: led.c

void led(int i)

ve.h

Toggles P05 used for led.

Var: i - Led on or off

Reference: led.c

void delay0(unsigned int t)

ve.h

Approximate loop delay. Does not use timer.

Var: m – Delay using simple for loop up to t.

Reference:

Summary of Contents for V104

Page 1: ... C Programmable 16 bit Microprocessor Module Based on the NEC V25 with a PC 104 Bus Technical Manual 1950 5th Street Davis CA 95616 USA Tel 530 758 0180 Fax 530 758 0181 Email sales tern com http www tern com ...

Page 2: ...w tern com Important Notice TERN is developing complex high technology integration systems These systems are integrated with software and hardware that are not 100 defect free TERN products are not designed intended authorized or warranted to be suitable for use in life support applications devices or systems or in other critical applications TERN and the Buyer agree that TERN will not be liable f...

Page 3: ...CD interface Figure 1 1 Functional block diagram of the V104 Measuring 4 0 x 3 5 x 0 5 inches the V104 offers a complete C C programmable computer system with a 16 bit high performance CPU NEC V25 and operates at 8 MHz with zero wait states Optional features include up to 512K EPROM Flash and up to 512K battery backed SRAM A 512 byte serial EEPROM is included on board An optional real time clock p...

Page 4: ...ed DC with VE232 16 bit CPU NEC V25 8 MHz Intel 80x86 compatible C C programmable ROM and SRAM up to 1MB 512 byte EEPROM or up to 2KB and 256 bytes built in CPU SRAM Five external interrupts 24 bi directional digital I O lines 8 comparator inputs Two 16 bit timers one 16 bit time base counter Two 16 bit counters or DMA The counter can count external signal rising edges up to 500 KHz Two high speed...

Page 5: ...easy steps as shown in the block diagram below Replace Debug ROM project is complete STEP 3 Test V104 in the field away from PC STEP 2 Application program resides in the battery backed SRAM Debug and run application with remote Debugger STEP 1 Serial link PC and V104 program in C C Burn application ROM You can program the V104 from your PC via serial link with an RS232 interface Your C C program c...

Page 6: ...ld test is complete application ROMs can be produced to replace the DEBUG ROM The HEX or BIN file can be easily generated with the makefile provided You may also use the DV Kit or ACTF Kit to download your application code to on board Flash The three steps in the development of a C C application program are explained in detail below 1 4 1 Step 1 STEP 1 Debugging Write your C C application program ...

Page 7: ...or HEX file make production ROMs or download your program to FLASH via ACTF If you are happy with your Step Two test you can go back to your PC to generate your application ROM to replace the DEBUG ROM TDREM_V25 You need to change DEBUG 1 to DEBUG 0 in the makefile You need to have the DV Kit to complete Step Three Please refer to the Tutorial of the Technical Manual of the EV DV Kit for further d...

Page 8: ...115 200 baud V104 controller with DEBUG ROM TDREM_V25 VE232 interface board DB9 IDE10 PC V25 serial cable RS232 DB9 connector for PC COM port and IDC 2x5 connector for controller center negative wall transformer 9V 500 mA NOTE the VE232 is not needed if you are using the V104 installed on another controller 1 6 2 Minimum Software Requirements TERN EV DV Kit installation diskettes PC software envir...

Page 9: ...troller to your PC For the V104 the VE232 must be used to supply regulated power and RS232 drivers to the V104 If you are using the V104 installed on another controller please refer to the technical manual for that controller for installation information 2 2 1 Connecting the VE232 to the V104 VE232 H1 J2 PC 104 Bus ROM V25 CPU RAM LCD PPI SCC AD DA RTC Figure 2 1 Before installing the VE232 on the...

Page 10: ...V104 is linked to the PC via a serial cable PC V25 The TDREM_V25 DEBUG ROM communicates through SER0 by default Install the 5x2 IDC connector on the SER0 header of the VE232 IMPORTANT Note that the red side of the cable must point to pin 1 of the VE232 H1 header The DB9 connector should be connected to one of your PC s COM Ports COM1 or COM2 V104 VE232 SER0 SER1 or COM2 To COM1 Indication of pin 1...

Page 11: ...transformer 9V DC output to the VE232 DC power jack The on board LED should blink twice and remain on after the V104 is powered on or reset Figure 2 4 PC 104 Bus ROM V25 CPU RAM LCD PPI SCC AD DA RTC VE232 Figure 2 4 The LED blinks twice after the V104 is powered on or reset ...

Page 12: ...4 J2 5 should be high 5V Write a 0 to P0 data register bit 5 the P05 pin on the V104 J2 5 should be low 0V Some I O lines are used by the V104 system as listed below P00 I O EEPROM U7 pin 6 clock SCL P01 I O EEPROM U7 pin 5 data SDA P02 I O J10 pin 19 If low jump to application code which starting address is defined in the on board EEPROM 0x10 to 0x13 P03 I O J7 pin 1 HWD Hit watchdog P04 I O WDO ...

Page 13: ...nstead After ve_init void the initial register control bytes are written into EEPROM You may use these image registers to determine the status of the port You may also need to update these registers in your applications The port0 2 are initialized by the ve_init void as listed below void ve_init void pokeb 0xfff0 0x02 0x80 Set PMC0 P07 CLK pokeb 0xfff0 0x01 0xd7 Set PM0 for input P05 LED P03 HWD o...

Page 14: ...0 Every rising edge input signal on J1 pin 36 P20 DR0 will decrement the counter 0 Every rising edge input signal on J2 pin 17 P23 will decrement the counter 1 Be aware of P20 is also used as LD signal for the 12 bit DAC An interrupt will occur after counting to zero You need an interrupt service route to serve the counter interrupt For more detail please see a sample program in TERN disk a sample...

Page 15: ...tion programs for SER0 The application programs can be combined and downloaded via either serial channel Application program using both SER0 and SER1 can run at the same time but not debug at the same time 3 2 6 Halt and Stop Mode The V104 is an ideal core module for low power consumption applications such as a battery operated instrument V25 has two standby modes which are set by halt and stop In...

Page 16: ...O u tp u t I n p u t M o d e 0 M o d e 1 M o d e 2 1 X C o m m a n d S e le c t 0 1 B it m a n ip u la tio n M o d e S e le c t Figure 3 2 Mode Select Command Word The V104 maps U11 the 82C55 uPD71055 in I O space to 0xC100 to 0xC103 The Command Register 0xC103 Port 0 0xC100 Port 1 0xC101 Port 2 0xC102 The following code example will set all ports to output mode outportb 0xC103 0x80 Mode 0 all out...

Page 17: ...lock RTC72421 EPSON U4 is mapped in the I O address space 0x8000 0xbffff It must be backed up with a lithium coin battery The RTC may be accessed via software drivers rtc_init or rtc_rd see Chapter 4 Details are listed in Appendix D 3 3 4 UART SCC2691 The UART SCC2691 Signetics U8 is mapped in the I O address space 0xc000 0xc0ff The SCC2691 has a full duplex asynchronous receiver transmitter a qua...

Page 18: ...failure Warning and Battery Backup If a jumper is put on the J4 1 2 then the NMI is connected to the PFO Power Failure Output pin of the MAX691 When the power failure is sensed by the PFI pin of the MAX691 lower than 1 3 V Figure 3 1 the PFO pulls NMI low and an NMI interrupt occurs before the power failure occurs You may design a NMI service routine to take protect actions before the 5V drops and...

Page 19: ...rom logic and supply noise A switched capacitor design allows low error conversion over the full operating temperature range The analog input signal source impedance should be less than 50Ω and capable of slewing the analog input voltage into a 60 pF capacitor You may read the ADC with the function in the library ce_ad12 ch In order to operate the TLC2543 five V25 I O lines are used as listed belo...

Page 20: ...r 3 Hardware 3 9 J7 5x1 pin 1 2 Enable watchdog timer pin 3 4 Enable EEPROM write protection pin 4 5 no write protection J8 2x1 Reset J9 2x1 SCC2691 MPO and MPI H1 8x2 LCD interface H2 2x1 UART SCC2691 MPO and MPI ...

Page 21: ...ace and a memory address space I O address space ranges from 0x0000 to 0xffff or 64 KB Memory address space ranges from 0x00000 to 0xfffff in real mode or 1 MB These are accessed differently and not all addresses can be translated and handled correctly by hardware I O and memory mappings are done in software to define how translations are implemented by the hardware Implicit accesses to I O and me...

Page 22: ... with user configured peripheral components When dealing with processor registers be sure to use the correct function Use outport if you are dealing with a 16 bit register inport inportb Arguments unsigned int address Return value unsigned int unsigned char data This function can be used to retrieve data from components in I O space You will find that most hardware options added to TERN controller...

Page 23: ...nvolving the interrupts the user should refer to chapter 4 of the NEC V25 CPU User s Manual TERN provides functions to enable disable all of the external interrupts The user can call any of the interrupt init functions listed below for this purpose The first argument indicates whether the particular interrupt should be enabled and the second is a function pointer to an appropriate interrupt servic...

Page 24: ...ical manual For a detailed discussion of the I O ports please refer to chapter 7 of the NEC V25 User s Manual Please see the sample program portx c in tern v25 samples ve You will also find that these functions are used throughout TERN sample files as most applications do find it necessary to re configure the PIO lines The functions port_wr and port_rd can be quite slow when accessing the Port I O...

Page 25: ...t all of port 2 is outputting low the peekb function will return a value of 0x00 A bitwise OR with the value 0x00 and the mask 0x08 equals 0x08 Port 2 now outputs 0x08 Example 4 4 Using bitwise AND to reset a single bit low set pin 23 low without modifying the other pins Assume settings are the same after executing Example 4 3 pokeb 0xfff0 0x10 unsigned char peekb 0xfff0 0x10 0xF7 Assuming the set...

Page 26: ...sults in a value 1 PTn Vth results in a value 0 All eight results from PT0 to PT7 are latched to the port T input latches The resulting 8 bit latch can be accessed by the function portt_rd void which returns the 8 bit result Vth can be changed by the function portt_wr char vref The variable vref 0 15 sets the reference voltage by the following equation Reference Vth vref 16 vref 0 sets Reference V...

Page 27: ...placed into the TMC0 TMC1 mode registers for configuring the two timers The argument md0 is the modulo timer count and t0 is the timer count void timer0_interrupt void timer1_interrupt Arguments unsigned char i void interrupt far timer0_isr Return values none The argument i enables the interrupt and timer0_isr or timer1_isr points to the interrupt service routine The interrupt service routine is c...

Page 28: ...year digit unsigned char wk Day of the week TIM int rtc_rd Arguments TIM r Return value int error_code This function places the current value of the real time clock within the argument r structure The structure should be allocated by the user This function returns 0 on success and returns 1 in case of error such as the clock failing to respond Void rtc_init Arguments char t Return value none This ...

Page 29: ... h in the tern v25 include directory The internal asynchronous serial ports are functionally identical SER0 is used by the DEBUG ROM provided as part of the TERN EV DV software kits for communication with the PC As a result you will not be able to debug code directly written for serial port 0 Two asynchronous serial ports are integrated in the NEC V25 CPU SER0 and SER1 Both ports have baud rates b...

Page 30: ...s used as a circular ring buffer as shown in Figure 4 1 However the transmit operation is interrupt driven ibuf in_tail ibuf isiz in_head Figure 4 1 Circular ring input buffer The input buffer ibuf buffer size isiz mode mode and baud rate baud are specified by the user with s1_init The mode is the setting value for the serial port control register A value of 0xC9 will set the serial port in the fo...

Page 31: ...l the data you specify After all data has been sent it will clear the busy flag and be ready for the next transmission The sample program ser1_0 c demonstrates how a protocol translator works It would receive an input HEX file from SER1 and translate every character to The translated HEX file is then transmitted out of SER0 This sample program can be found in tern 186 samples ve Software Interface...

Page 32: ... tail buffer pointers appropriately If you do not call one of the following functions however the driver interrupt for the appropriate serial port will be disabled which means that no values will be transmitted This allows you to control when you wish the transmission of data within the outbound buffer to begin Once the interrupts are enabled it is dangerous to manipulate the values of the outboun...

Page 33: ...ys the single byte versions of these functions are probably more appropriate Miscellaneous Serial Communication Functions One thing to be aware of in both transmission and receiving of data through the serial port is that TERN drivers only use the basic serial port communication lines for transmitting and receiving data Hardware flow control in the form of CTS Clear To Send and RTS Ready To Send i...

Page 34: ...ver be able to complete this process Over time this means data might be lost in the SCC as bytes overflow Special control registers are used to define how the SCC operates For a detailed description of registers MR1 and MR2 please see Appendix C of this manual In most TERN applications MR1 is set to 0x57 and MR2 is set to 0x07 This configures the SCC for no flow control RTS CTS not used checked no...

Page 35: ...rd you will need to disable receive while transmitting While transmitting you will also need to place the RS485 driver in transmission mode as well This is done by using scc_rts 1 This uses pin MPO multi purpose output found on the J1 header While you are receiving data the RS485 driver will need to be placed in receive mode using scc_rts 0 en485 Arguments int i Return value none This function set...

Page 36: ...A is 1 to indicate a framing error Bit B is 1 to indicate a parity error and bit C indicates an over run error 4 5 Functions in VEEE OBJ The 512 byte serial EEPROM 24C04 provided on board provides easy storage of non volatile program parameters This is usually an ideal location to store important configuration values that do not need to be changed often Access to the EEPROM is quite slow compared ...

Page 37: ...unction returns one byte of data from the specified address 4 6 V104 Sample Programs for DAC LCD The following sample programs supporting the DAC and LCD can be found in the c tern v25 samples v104 directory V_ct_da c V104_da c V104_dac c V104_lcd c V104_ppi c ...

Page 38: ...re in inches PC 104 Bus ROM V25 CPU RAM LCD PPI SCC AD DA RTC J3 AD DA header V25 Ports VE232 interface 3 50 4 00 3 325 3 733 0 317 3 825 0 125 3 850 0 358 2 225 PAL V104P1000 PAL V104P000 3 325 0 183 0 0 0 0 3 375 3 883 3 425 0 633 3 375 0 317 0 125 0 317 J5 24 I O lines ...

Page 39: ...V104 Appendix B VE232 Pin Layout B 1 Appendix B VE232 Pin Layout All dimensions are in inches ...

Page 40: ...nd 2 Register Addressing A2 A1 A0 READ RDN 0 WRITE WRN 0 0 0 0 MR1 MR2 MR1 MR2 0 0 1 SR CSR 0 1 0 BRG Test CR 0 1 1 RHR THR 1 0 0 1x 16x Test ACR 1 0 1 ISR IMR 1 1 0 CTU CTUR 1 1 1 CTL CTLR Note ACR Auxiliary control register BRG Baud rate generator CR Command register CSR Clock select register CTL Counter timer lower CTLR Counter timer lower register CTU Counter timer upper CTUR Counter timer upp...

Page 41: ... 1 110 2 134 5 3 150 4 300 5 600 6 1200 7 2000 8 2400 9 4800 A 7200 B 1800 C 19 2k D Timer E MPI 16x F MPI 1x CR Command Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Miscellaneous Commands Disable Tx Enable Tx Disable Rx Enable Rx 0 no command 8 start C T 1 reset MR pointer 9 stop counter 2 reset receiver A assert RTSN 3 reset transmitter B negate RTSN 4 reset error status C reset MPI ...

Page 42: ...xRDY 7 RxRDY FFULL ISR Interrupt Status Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MPI Pin Change MPI Pin Current State Not Used Counter Ready Delta Break RxRDY FFULL TxEMT TxRDY 0 no 1 yes 0 low 1 high 0 no 1 yes 0 no 1 yes 0 no 1 yes 0 no 1 yes 0 no 1 yes IMR Interrupt Mask Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MPI Change Interrupt MPI Level Interrupt Not Used Co...

Page 43: ...1 0 9 1 day digit register 0 1 1 1 D10 d20 d10 0 3 10 day digit register 1 0 0 0 MO1 mo8 mo4 mo2 mo1 0 9 1 month digit register 1 0 0 1 MO10 mo10 0 1 10 month digit register 1 0 1 0 Y1 y8 y4 y2 y1 0 9 1 year digit register 1 0 1 1 Y10 y80 y40 y20 y10 0 9 10 year digit register 1 1 0 0 W w4 w2 w1 0 6 Week register 1 1 0 1 Reg D 30s Adj IRQ Flag Busy Hold Control register D 1 1 1 0 Reg E t1 t0 INT S...

Page 44: ...ng 0x01 Board Type 00 VE 10 CE 01 BB 02 PD 03 SW 04 TD 05 MC 0x02 0x03 0x04 SER0_receive used by ser0 c 0x05 SER0_transmit used by ser0 c 0x06 SER1_receive used by ser1 c 0x07 SER1_transmit used by ser1 c 0x10 CS high byte used by ACTR 0x11 CS low byte used by ACTR 0x12 IP high byte used by ACTR 0x13 IP low byte used by ACTR 0x18 MM page register 0 0x19 MM page register 1 0x1a MM page register 2 0...

Page 45: ... READY pokeb 0xfff0 0x09 0xaf Set PM1 for input P14 RTS1 P16 RTS0 OUTPUT pokeb 0xfff0 0x12 0x00 Set P20 P27 for port mode pokeb 0xfff0 0x11 0xf7 Set PM2 for input P23 EN485 output Reference led c void ve_reset void ve h Resets the V25 processor void delay_ms int m ve h Approximate microsecond delay Does not use timer Var m Delay in approximate ms Reference led c void led int i ve h Toggles P05 use...

Page 46: ...n on the MAX691 void port_init char p char pmc char pm ve h Initializes I O port mode control and port mode Var p port 0 1 or 2 The PMC and PM variables define each pin of the 8 bit port selected For example PM 0xf0 would set bits 0 3 as low and bits 4 7 as high pmc CONTROL or I O mode 0 I O 1 CONTROL pm I O pin as input or output 0 output 1 input Reference portx c void port_wr char p char dat ve ...

Page 47: ...bit 1 PTn Vref where PTn is the input voltage and Vref is the selected threshold voltage Reference portt c void outport int portid int value dos h Writes 16 bit value to I O address portid Var portid I O address value 16 bit value void outportb int portid int value dos h Writes 8 bit value to I O address portid Var portid I O address value 8 bit value int inport int portid dos h Reads from an I O ...

Page 48: ...g sequence is the following time 0 weekday time 1 year10 time 2 year1 time 3 mon10 time 4 mon1 time 5 day10 time 6 day1 time 7 hour10 time 8 hour1 time 9 min10 time 10 min1 time 11 sec10 time 12 sec1 unsigned char time 2 9 8 0 7 0 1 1 3 1 0 2 0 Tuesday July 01 1998 13 10 20 Reference rtc_init c int rtc_rd TIM r ve h Reads from the real time clock Var r Struct type TIM for all of the RTC data typed...

Page 49: ... i void interrupt far intp0_isr void intp1_init unsigned char i void interrupt far intp1_isr void intp2_init unsigned char i void interrupt far intp2_isr Initialization for interrupts 0 through 2 and NMI Non Maskable Interrupt Var i 1 enable 0 disable int _isr pointer to interrupt service Reference intpx c void s0_init char m char b unsigned char ibuf int isiz ser0 h unsigned char obuf int osiz CO...

Page 50: ...ointer to output buffer array osiz ouput buffer size c pointer to serial port structure See VE H for COM structure m1 bit Definition 7 RxRTS receiver request to send control 0 no 1 yes 6 RxINT receiver interrupt select 0 RxRDY 1 FIFO FULL 5 Error Mode Error Mode Select 0 Char 1 Block 4 3 Parity Mode 00 with 01 Force 10 No 11 Special 2 Parity Type 0 Even 1 Odd 1 0 bits 00 5 01 6 10 7 11 8 m2 bit De...

Page 51: ... output with interrupt isr Var str pointer to output character string c pointer to serial port structure Reference ser1_sin c int serhit0 COM c ser0 h int serhit1 COM c ser1 h int serhit_scc COM c scc h Checks input buffer for new input characters Returns 1 if new character is in input buffer else 0 Var c pointer to serial port structure Reference s0_echo c s1_echo c s1_0 c unsigned char getser0 C...

Page 52: ... less characters than the length requested str will contain only the remaining characters from the buffer Appends a 0 character to the end of str Returns the retrieved string length Var c pointer to serial port structure len desired string length str pointer to output character string Reference ser1 h ser0 h for source code ...

Page 53: ...aphic LCD This demo program gives some of the basic graphic libraries that can be expanded to fulfill many of the graphic needs the user might have For V104 U5 PAL V104LCD0 PDS H1 pin 15 LCD2 IORD H1 pin 16 RST added wire to V104 U4 pin15 Special Cable made for converting V104 H1 signals to GLCD header GLCD240x64 V104 H1 pin 20 GND pin 19 D7 D6 pin1 D7 D6 pin2 D5 D4 D5 D4 D3 D2 D3 D2 D1 D0 D1 D0 R...

Page 54: ...A1 P24 D12 PT6 RST P12 D24 PT7 D0 P15 259 P25 VCC MemCard A 1 J10 20 P27 P06 P25 PT6 P15 GND VCC P24 PT7 P12 J3 1 20 V104 CS8900 U1 J1 J2 U10 U12 U16 U15 U11 U9 232 U5 ADC U6 ADC U7 LTC 2400 REF ADC U8 U3 LTC 2400 LTC 2400 LTC 2400 LTC 2400 LTC 2400 HC259 U2 U4 U13 J4 U17 H1 H3 MemCard A PC 104 Bus ROM V25 CPU RAM LCD PPI SCC AD DA RTC PAL V104P1000 PAL V104P000 J5 24 I O lines J10 J3 V104 V104 MM...

Page 55: ...20 HDRD20 D1 D2 D3 R W AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 C10 DIPCAP VRAM A2 A3 IORD GND AD9 AD10 REF GND P27 C8 DIPCAP D7 D6 D5 D4 PT4 PT3 PT2 PT1 PT0 P17 P16 P15 P14 P13 P12 PT5 AD5 AD6 AD7 AD8 D0 D1 D2 D3 A4 A3 A2 A1 A0 D1 D2 D3 D4 D5 D6 D7 A11 A10 A9 A8 A7 A6 A5 P11 P27 P26 P25 P24 P23 NMI IOWR RST WR 40 P07 41 P06 42 P05 43 P04 44 NC 1 P03 2 P02 3 P01 4 P00 5 RD 6 R S T 3 9 D 0 3 8 D 1 ...

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