Chapter 3: Hardware
V104
3-2
PT5
INPUT
J10 pin 9.
PT6
INPUT
J10 pin 8.
PT7*
INPUT
J10 pin 7.
P00, P01, P05, P07, P17, P24-27 are used by system and ADC. While using the DEBUG EPROM, P02 is
used to select STEP 1 (DEBUG mode) or STEP 2 (standalone mode) during the power on or reset, see Fig
1.2a for detail. P17 is assigned as RDY signal for inserting more wait states in order to interface with slow
LCD modules. If you do not need LCD functions, you may assign P17 as a I/O function line and cutoff the
pin on the U5 PAL pin 12. I/O lines with * marked are optionally used by system or application. For
example, P05 is used for on board LED control, but P05 is also can be used as for application, if you do not
need LED. P03 can be used to hit watchdog or can be used for your application, if you do not use watchdog.
Due to SFR registers of PMC0-2, PM0-2 are write only, image registers are assigned to locations in the on
board EEPROM at:
PM0
0x08
ee_rd(0x08); or ee_wr(0x08, pm0);
PMC0 0x09
ee_rd(0x09); or ee_wr(0x09, pmc0);
PM1
0x0a
ee_rd(0x0a); or ee_wr(0x0a, pm1);
PMC1 0x0b
ee_rd(0x0b); or ee_wr(0x0b, pmc1);
PM2
0x0c
ee_rd(0x0c); or ee_wr(0x0c, pm2);
PMC2 0x0d
ee_rd(0x0d); or ee_wr(0x0d, pmc2);
The ee_rd() and ee_wr() functions are very slow. The EEPROM is only modified by the ve_init();. Other
functions may change the PMCx and PMx registers without modifying the EEPROM. If you need fast
access the image registers, you may use SRAM variables instead.
After ve_init(void);, the initial register control bytes are written into EEPROM. You may use these image
registers to determine the status of the port. You may also need to update these registers in your
applications. The port0-2 are initialized by the ve_init(void) as listed below:
void ve_init(void){
pokeb(0xfff0,0x02,0x80);
/* Set PMC0 P07=CLK */
pokeb(0xfff0,0x01,0xd7);
/* Set PM0 for input, P05=LED P03=HWD
output */
pokeb(0xfff0,0x0a,0x80);
/* Set PMC1 P17 for READY */
pokeb(0xfff0,0x09,0xaf);
/* Set PM1 for input, P14=RTS1,P16=RTS0
OUTPUT */
pokeb(0xfff0,0x12,0x00);
/* Set P20-P27 for port mode */
pokeb(0xfff0,0x11,0xf7);
/* Set PM2 for input, P23=EN485 output */
}
The port data registers can be read and write. In order to modify only one bit, you need to read back the
data byte from that data register first, then do OR/AND operation on that bit.
For example, you can manipulate P05 to low or high with these functions:
pokeb(0xfff0,0x00,(unsigned char) (peekb(0xfff0,0)&0xdf));
/* Set
P05=low */
pokeb(0xfff0,0x00,(unsigned char) (peekb(0xfff0,0)|0x20));
/* Set
P05=high */
3.2
Memory Mapped Devices
All CPU-on-chip peripherals are memory mapped. They are controlled by a bank of 256-byte special
function registers (SFRs). SFRs can be relocated within 1 M-byte V25 memory space. Most of the CPU-on-
chip peripherals can be reached from J2 and J10.
3.2.1
Interrupts
V25 has a built-in high performance interrupt controller that can control multiple processing of 17 interrupt
sources. Five of these interrupt sources, NMI, INTP0, INTP1, INTP2, and INT are external and accessible
via memory mapped SFRs. The MAX691/LTC691 PFO (Power Failure Output) pin is connected to NMI
