V104
Chapter 3: Hardware
3-3
via J4 pin 2-3. The user may connect the PFI (Power Failure Input) pin of MAX691 to an external voltage
divider to monitor the power voltage level (Figure 3.1). The PFI pin has been pulled high to VCC with a
10K resistor on the V104. When the external DC power drops and the voltage on the PFI (J2 pin 8) is less
than 1.3 V, the MAX691 will pull down PFO pin, and NMI will occur. You can write a NMI interrupt
service routine to meet your requirements (see Chapter 4, “External Interrupts” for setting an NMI service
routine). V25 CPU has three different methods of responding to an interrupt: vector interrupt functions,
register bank switching functions, and macro service functions. V104 uses vector interrupt. Refer to Chapter
4 and the NEC V25 User's Manual for information about writing interrupt service routines.
External Resistor Divider for Power Failure Detection
47K
2K
PFI of MAX691
(1.3 V min)
(8.35 V min)
9-14 V
10K
VCC = +5V
PT7
Figure 3.1 Using PFI to monitor power voltage level
3.2.2
Comparator Input Port (PORTT)
Port T is an 8-bit comparator input port. The threshold voltage VTH can be fixed to VCC or connected to a
variable voltage source. Software can set the reference voltage to one of 16 levels (1/16xVTH to
16/16xVTH). It provide users with an easy and inexpensive way to measure analog input signals. VTH is
pulled high to VCC via a 10K resistor on board.
3.2.3
External Event Counters / DMA
V25 has two DMA channels, DMA0 and DMA1. The DMA controllers can be used as 16-bit external event
counters. After you set a 16-bit counter value into counter 0 or counter 1 with
counter0_init(unsigned int cnt0); or counter0_init(unsigned int cnt0);
Every rising edge input signal on J1 pin 36 (P20=/DR0) will decrement the counter 0. Every rising edge
input signal on J2 pin 17 (P23) will decrement the counter 1. Be aware of P20 is also used as /LD signal for
the 12-bit DAC. An interrupt will occur, after counting to zero. You need an interrupt service route to serve
the counter interrupt. For more detail, please see a sample program in TERN disk,
a:\samples\ve\ve_count.c.
The V104 supports DMA0 only. There are four different DMA transfer modes, selectable by software. For
memory to memory DMA transfer, the DMAAK0 is not active. For memory to I/O DMA transfer, the
DMAAK0 asserts every DMA cycle. P21 and P20 can be used as I/O pins. For more information refer to
Section 6 of the V25 User's Manual.
3.2.4
Clock and Timers
A built-in clock generator supplies various clocks to the CPU and peripheral hardware. The V104 uses a 16
MHz crystal. Default system clock output after initialization is 8 MHz on CLK line (pin 40 of J1). One
clock cycle is 125 ns. The normal bus cycle requires two clock cycles, which is 250 ns. With built-in wait
state generation, up to 2 wait states can be inserted. Additional wait states can be inserted by using the RDY
line. With the default initialization of 2 wait states, EPROMs of 120 ns to 150 ns can be used. More delays
may be required to support slow I/O devices, such as LCD (Liquid Crystal Display).
The time base counter operates continuously since the V104 is powered on. It provides clock signals for
two 16-bit timers, baud rate generator, refresh timing, refresh address, and time base interrupt request flag.
CLKOUT(P07) and /REFRQ are two outputs of the time base counter. The CLKOUT output to peripheral
hardware. /REFRQ may be used to refresh DRAM in user applications. A time base interrupt is generated at
4 different intervals, 128 us, 1.024 ms, 8.192 ms, and 131.072 ms, selectable by software.
