Chapter 3: Hardware
V104
3-8
3.4.2
EEPROM
A serial EEPROM of 128 bytes (24C01), 512 bytes (24C04), or 2K bytes (24C16) can be installed in U7.
The V25-Engine uses the P00=SCL (serial clock) and P01=SDA (serial data) to interface with the
EEPROM. The EEPROM can be used to store important data such as a node address, calibration
coefficients, and configuration codes. It typically has 1,000,000 erase/write cycles, and the data retention is
more than 40 years. EEPROM can be read and written to by simply calling the functions ee_rd() and
ee_wr().
3.4.3
12-bit ADC (TLC2543)
The TLC2543 is a 12-bit, switched-capacitor, successive-approximation, 11 channels, serial interface,
analog-to-digital converter. It has three control inputs (/CS=P27; CLK=P24; DIN=P25) and is designed for
communication with a host through a serial tri-state output(DOUT=P26). If P27 is low, the TLC2543 will
have output on P26. If P27 is high, the TLC2543 is disabled and P24, P25, P26 are free. P27 is pulled high
by a 10K resistor on board. The TLC2543 has an on-chip 14 channel multiplexer that can select any one of
11 inputs or any one of three internal self-test voltages. The sample-and-hold function is automatic. At the
end of conversion, the end-of-conversion output goes high to indicate that conversion is complete.
TLC2543 features differential high-impedance inputs that facilitate ratiometric conversion, scaling, and
isolation of analog circuitry from logic and supply noise. A switched-capacitor design allows low-error
conversion over the full operating temperature range. The analog input signal source impedance should be
less than 50
Ω
and capable of slewing the analog input voltage into a 60 pF capacitor.
You may read the ADC with the function in the library: ce_ad12(ch);
In order to operate the TLC2543, five V25 I/O lines are used as listed below:
/CS
Chip select = P27, high to low transition enables DOUT, DIN and CLK.
low to high transition disables DOUT, DIN and CLK.
DIN
P25, serial data input
DOUT
P26, 3-state serial data output.
CLK
I/O clock = P24
REF+
Upper reference voltage(normally VCC)
REF-
Lower reference voltage(normally GND)
VCC
Power supply, +5 V input
GND
Ground
The analog inputs AD0 to AD10, REF+, GND, and VCC are available at J3 connector.
3.4.4
12-bit DAC (MAX537)
The MAX537 combines four 12-bit, voltage output digital to analog converters and four precision output
amplifiers in a 16 pin chip. The MAX537 operates with
±
5V power supply. Each DAC has a double-
buffered input. A 16-bit serial word is used to load data into input/DAC register. The V104 uses P20=/LD,
P21=DAC /CS, P24=SCLK, and P25=SDI to operate the MAX537. The REF+ of the MAX537 is 2.5V
provided by U14. You may write the DAC with the function in the library: v104_da12(ch, dat);
3.5
Jumpers and Headers
There are 14 jumpers and connectors on the V104.
Name Size
Function
J1
32x2
PC/104 compatible bus
J2
10x2
VE232 interface
J3
10x2
Analog inputs, analog outputs and reference
J4
3x1
VOFF, /NMI and /PFO
J5
25x2
24 bi-directional I/O pins, +5V and GND
J6
12x1
Memory selection, see Figure 3.3
