TSoM Evaluation
Kit User Manual
39
www.terasic.com
July 26, 2019
memory size of the DDR3 used in this test is 1 GB.
System Block Diagram
shows the function block diagram of this demonstration. The DDR3 controller uses 50
MHz as a reference clock. It generates one 300MHz clock as memory clock from the FPGA to the
memory.
Figure 6-5 Block Diagram of the DDR3_RTL Demonstration
Intel DDR3 SDRAM Controller with UniPHY
To use intel DDR3 controller, please perform the three major steps below:
1.
Create correct pin assignments for DDR3.
2.
Setup correct parameters in the dialog of DDR3 controller.
Design Tools
Quartus Prime v17.1
Demonstration Source Code:
Project Directory: Demonstration\FPGA\DDR3
Bit Stream: DDR3\output_files\TSOM_top.sof
Demonstration Batch File:
Demo Batch File Folder: DDR3\demo_batch
The demo batch file includes following files:
Summary of Contents for TSOM
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