Terasic TSOM Manual Download Page 21

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TSoM Evaluation
Kit User Manual

www.terasic.com

July 26, 2019

Chapter 4

HPS Fabric Components

This chapter describes the interfaces connected to TSoM Based Board. Users can access these
interfaces via the HPS processor on the TSoM module.

The board supports a RJ-45 connector, which is provided by the TsoM Based Board.

Figure 4-1

shows the connections between the TSoM module, 260 Pin edge connector and RJ-45 connector.

The pin assignment of Ethernet PHY and HPS is listed in

Table 4-1

Figure 4-1 The connections between the TSoM module, 260 Pin edge connector and

RJ-45 connector

Table 4-1 The pin assignment of Ethernet PHY and HPS on the TSoM module

Signal Name

FPGA Pin No.

Description

I/O Standard

HPS_ENET_TX_EN

A12

GMII and MII transmit enable

3.3V

HPS_ENET_TX_DATA[0]

A16

MII transmit data[0]

3.3V

HPS_ENET_TX_DATA[1]

J14

MII transmit data[1]

3.3V

HPS_ENET_TX_DATA[2]

A15

MII transmit data[2]

3.3V

HPS_ENET_TX_DATA[3]

D17

MII transmit data[3]

3.3V

HPS_ENET_RX_DV

J13

GMII and MII receive data valid

3.3V

HPS_ENET_RX_DATA[0]

A14

GMII and MII receive data[0]

3.3V

HPS_ENET_RX_DATA[1]

A11

GMII and MII receive data[1]

3.3V

HPS_ENET_RX_DATA[2]

C15

GMII and MII receive data[2]

3.3V

HPS_ENET_RX_DATA[3]

GMII and MII receive data[3]

3.3V

HPS_ENET_RX_CLK

J12

GMII and MII receive clock

3.3V

HPS_ENET_MDIO

E16

Management Data

3.3V

Summary of Contents for TSOM

Page 1: ......

Page 2: ...ce 9 C Ch ha ap pt te er r 3 3 9 3 1 Settings of FPGA Configuration Mode 9 3 2 Configuration of Cyclone V SoC FPGA on TSoM evalu ation kit 11 3 3 Board Status Elements 18 3 4 Board Reset Elements 18 Chapter 4 HPS Fabric Components 20 C Ch ha ap pt te er r 4 4 20 4 1 Ethernet RJ45 20 4 2 USB OTG Connector 21 4 3 UART to USB 22 4 4 Micro SD Card 23 4 5 QSPI Flash DNI 23 4 6 Raspberry Pi 2x13 GPIO 24...

Page 3: ...ut 31 5 4 HDMI TX Interface 33 Chapter 6 Examples For FPGA 35 C Ch ha ap pt te er r 6 6 35 6 1 HDMI TX 35 6 2 DDR3_RTL 38 Chapter 7 Programming the EPCS Device 41 Chapter 8 eMMC Programming 53 Appendix 61 C Ch ha ap pt te er r 7 7 61 C Ch ha ap pt te er r 8 8 61 C Ch ha ap pt te er r 9 9 61 9 1 Revision History 61 ...

Page 4: ... and JTAG configuration function for TSoM it connects the FPGA and HPS fabric I O of TSoM to many application interfaces such as USB Ethernet HDMI Micro SD card and so on it expanded the FPGA I O which are connected to 260 pin edge connector to a variety of applications The TSoM based board also provides USB Blaster II circuit users can configure and debug the FPGA on TSoM through the JTAG interfa...

Page 5: ...kage contains all the documents and supporting materials associated with TSoM Evaluation Kit including the user manual reference designs and device datasheets Users can download this design package from the link http TSoM terasic com cd 1 1 3 3 G Ge et tt ti in ng g H He el lp p Here are the addresses where you can get help if you encounter any problems Terasic Technologies 9F No 176 Sec 2 Gongdao...

Page 6: ...design characteristics of the board 2 2 1 1 L La ay yo ou ut t a an nd d C Co om mp po on ne en nt ts s Figure 2 1 and Figure 2 2 shows a photograph of the TSoM Evaluation Kit TSoM module board and TSOM Based Board It depicts the layout of the board and indicates the location of the connectors and key components Figure 2 1 TSoM Evaluation Kit Top View ...

Page 7: ...9 Figure 2 2 TSoM Evaluation Kit Back View 2 2 2 2 B Bl lo oc ck k D Di ia ag gr ra am m Figure 2 3 is the block diagram of the TSoM Evaluation Kit and Figure 2 4 shows the block diagram of the TSoM Module board Figure 2 3 Block diagram of the TsoM evaluation kit ...

Page 8: ...110K LEs Interface DDR4 Edge include 3 3V power source Dimension 50 mm x 70 mm FPGA Fabric side DDR3 SDRAM 1GB 32bit 303MHz Soft IP LVDS Transmitter x15 LVDS Receiver x17 pairs GPIO x3 Total GPIO x67 EPCS64 HPS Fabric side Boot Selection DIP Switch boot from eMMC or MicroSD Card DDR3 SDRAM 1GB 32bit 400MHz USB 2 0 PHY Gigabit Ethernet PHY 3 3V GPIO x25 Can UART SPI I2C Trace Buses 1 5V GPI x4 Inpu...

Page 9: ... x 2 HDMI TX v1 4 1080P Full HD Compatible with HDCP v1 4 TMD Header x2 support 16 GPIO ADC 8 channel 12 bit 500Ksps HPS Fabric MicroSD Socket Optional 512Mb QSPI FLASH Need to rework Boot Selection resistor on Module USB to UART USB OTG PHY Mini B Connector Ethernet RJ45 Connector USB OTG Micro AB Connector 2x13 GPIO include I2C UART SPI Compatible with Raspberry Pi Expansion IO ...

Page 10: ...L 4 0 on the TSoM module is FPPx32 mode See Figure 3 1 It means that when the TSoM evaluation kit is power on the FPGA is configured from the HPS fabric When the software on the HPS is running the FPGA can be configured via HPS Figure 3 1 TsoM module is setting to FPPx32 mode As shown in the Figure 3 2 there are 3 storage devices can be supported on TSoM evaluation kit to boot HPS SD Card QSPI fla...

Page 11: ...ers can switch between the two boot devices through the switch SW1 on the TSOM module board See Figure 3 3 The factory default boot device is SD card interface SW1 is set to ON position Figure 3 3 eMMC SD Card select switch The QSPI Flash is the option function and don t install on the board Users can apply it on their own if needed After the user installs the QSPI flash user can adjust the SW2 on...

Page 12: ...SoM module manual for EPCS part Modify the SW2 on the TSoM module to AS mode See Figure 3 5 Figure 3 5 SW2 Setting Resistors AS Mode 3 3 2 2 C Co on nf fi ig gu ur ra at ti io on n o of f C Cy yc cl lo on ne e V V S So oC C F FP PG GA A o on n T TS So oM M e ev va al lu u a at ti io on n k ki it t There are two types of programming method supported by TSoM evaluation kit 1 JTAG programming It is n...

Page 13: ...he Cyclone V SoC FPGA JTAG Chain on TSoM Evaluation Kit The FPGA device can be configured through JTAG interface on TSoM evaluation kit board but the JTAG chain must form a closed loop which allows Quartus II programmer to the detect FPGA device Figure 3 6 illustrates the JTAG chain on TSoM evaluation kit board In addition the TSoM evaluation kit has one external JTAG Header J7 reserved for users ...

Page 14: ...Programmer Window If it is not already turned on turn on the DE SoC USB 1 option under currently selected hardware and click Close to close the window See Figure 3 8 Figure 3 8 Hardware Setting Return to the Quartus II programmer and click Auto Detect as circled in Figure 3 9 ...

Page 15: ...ice in JTAG mode If the device is detected the window of the selection device is opened Please select detected device associated with the board and click OK to close the window as circled in Figure 3 10 Figure 3 10 Select 5CSEBA6 device Both FPGA and HPS are detected as shown in Figure 3 11 ...

Page 16: ...uation Kit User Manual 15 www terasic com July 26 2019 Figure 3 11 FPGA and HPS detected in Quartus programmer Right click on the FPGA device and open the sof file to be programmed as highlighted in Figure 3 12 ...

Page 17: ... be programmed into the FPGA device Select the sof file to be programmed as shown in Figure 3 13 Figure 3 13 Select the sof file to be programmed into the FPGA device Click Program Configure check box and then click Start button to download the sof file into the FPGA device as shown in Figure 3 14 ...

Page 18: ...ically loaded from the serial configuration device chip into the FPGA when the board is powered up Users need to use Serial Flash Loader SFL to program the serial configuration device via JTAG interface The FPGA based SFL is a soft intellectual property IP core within the FPGA that bridge the JTAG and Flash interfaces The SFL Megafunction is available in Quartus II Figure 3 15 shows the programmin...

Page 19: ...V power is active LED10 5 V Power Illuminate when 5V power is active LED4 JTAG_TX Illuminate when data is transferred from JTAG to USB Host LED5 JTAG_RX Illuminate when data is transferred from USB Host to JTAG TXD1 UART TXD Illuminate when data is transferred from FT232R to USB Host RXD1 UART RXD Illuminate when data is transferred from USB Host to FT232R 3 3 4 4 B Bo oa ar rd d R Re es se et t E...

Page 20: ...ation kit Board Reference Signal Name Description Button1 TSoM Based board HPS_RESET_N Cold reset to the HPS Ethernet PHY and USB host device Active low input which resets all HPS logics that can be reset KEY1 TSoM Module board HPS_WARM_RST_N Warm reset to the HPS block Active low input affects the system reset domain for debug purpose Figure 3 18 HPS reset tree on TSoM evaluation kit board ...

Page 21: ...e 260 Pin edge connector and RJ 45 connector Table 4 1 The pin assignment of Ethernet PHY and HPS on the TSoM module Signal Name FPGA Pin No Description I O Standard HPS_ENET_TX_EN A12 GMII and MII transmit enable 3 3V HPS_ENET_TX_DATA 0 A16 MII transmit data 0 3 3V HPS_ENET_TX_DATA 1 J14 MII transmit data 1 3 3V HPS_ENET_TX_DATA 2 A15 MII transmit data 2 3 3V HPS_ENET_TX_DATA 3 D17 MII transmit d...

Page 22: ... RX TX H L OFF ON 100 Link No Activity H Toggle OFF Blinking 100 Link Activity RX TX L L ON ON 10 Link No Activity Toggle Toggle Blinking Blinking Link Activity RX TX 4 4 2 2 U US SB B O OT TG G C Co on nn ne ec ct to or r The board has an USB interfaces using the SMSC USB3300 controller which is provided by TsoM Based Board A SMSC USB3300 device in a 32 pin QFN package device is used to interface...

Page 23: ...V HPS_USB_NXT D5 Throttle the Data 3 3V HPS_USB_STP C5 Stop Data Stream on the Bus 3 3V 4 4 3 3 U UA AR RT T t to o U US SB B The board has one UART interface connected for communication with the HPS on the TsoM module This interface doesn t support HW flow control signals The physical interface is implemented by UART USB onboard bridge from a FT232R chip to the host with an USB Mini B connector M...

Page 24: ...the HPS 260 Pin edge connector and Micro SD card socket Table 4 5 lists the pin assignment of Micro SD card socket to the HPS Figure 4 4 Connections between the HPS 260 Pin edge connector and and SD card socket Table 4 5 Pin Assignment of Micro SD Card Socket Signal Name 260 pin Edge Connector Pin No FPGA Pin No Description I O Standard HPS_SD_CLK PIN_113 PIN_B8 HPS SD Clock 3 3V HPS_SD_CMD PIN_11...

Page 25: ...gnal names are from the device datasheet and directions are relative to the Cyclone V SoC FPGA Figure 4 5 Connections between the HPS 260 Pin edge connector and QSPI Flash Table 4 6 Pin Assignment of QSPI Flash Signal Name 260 pin Edge Connector Pin No FPGA Pin No Description I O Standard HPS_FLASH_DATA0 PIN_99 PIN_A8 HPS FLASH Data0 3 3V HPS_FLASH_DATA1 PIN_101 PIN_H16 HPS FLASH Data1 3 3V HPS_FL...

Page 26: ...i header In addition to being used as the HPS GPIO user can also use the corresponding peripheral controller in the HPS such as the SPI and UART interfaces Table 4 7 shows all the pin assignments of the Raspberry Pi 2x13 GPIO header Figure 4 6 Raspbery Pi 2x13 expansion header ...

Page 27: ...3 3V RPI_GPIO03 PIN_77 PIN_C18 RPI GPIO Connection 0 3 3V RPI_GPIO04 PIN_67 PIN_A21 RPI GPIO Connection 0 3 3V RPI_GPIO07 PIN_87 PIN_A17 RPI GPIO Connection 0 3 3V RPI_GPIO08 PIN_85 PIN_ J17 RPI GPIO Connection 0 3 3V RPI_GPIO09 PIN_83 PIN_B18 RPI GPIO Connection 0 3 3V RPI_GPIO10 PIN_81 PIN_C17 RPI GPIO Connection 0 3 3V RPI_GPIO11 PIN_79 PIN_A18 RPI GPIO Connection 0 3 3V RPI_GPIO14 PIN_93 PIN_B...

Page 28: ... RPI_GPIO18 PIN_69 PIN_K18 RPI GPIO Connection 0 3 3V RPI_GPIO22 PIN_73 PIN_J18 RPI GPIO Connection 0 3 3V RPI_GPIO23 PIN_95 PIN_B19 RPI GPIO Connection 0 3 3V RPI_GPIO24 PIN_97 PIN_C16 RPI GPIO Connection 0 3 3V RPI_GPIO25 PIN_89 PIN_H17 RPI GPIO Connection 0 3 3V RPI_GPIO27 PIN_71 PIN_A20 RPI GPIO Connection 0 3 3V ...

Page 29: ...push buttons connected The two push buttons named KEY0 and KEY1 coming out of the Schmitt trigger device are connected directly to the Cyclone V SoC FPGA The push button generates a low logic level or high logic level when it is pressed or not respectively Since the push buttons are debounced they can be used as clock or reset inputs in a circuit Figure 5 1 Connections between the push buttons and...

Page 30: ...nections between the slide switches and the Cyclone V SoC FPGA There are also two user controllable LEDs connected to the FPGA Each LED is driven directly and individually by the Cyclone V SoC FPGA driving its associated pin to a high logic level or low level to turn the LED on or off respectively Figure 5 4 shows the connections between LEDs and Cyclone V SoC FPGA Table 5 1 Table 5 2 and Table 5 ...

Page 31: ... Push button 1 3 3V Table 5 3 Pin Assignment of LEDs Signal Name 260 pin Edge Connector Pin No FPGA Pin No Description I O Standard LED0 PIN_205 PIN_AA26 LED 0 3 3V LED1 PIN_206 PIN_W12 LED 1 3 3V 5 5 2 2 T TM MD D H He ea ad de er r The board has two TMD connectors each connector has 8 user pins connected to the 260 pin Edge Connector to Cyclone V SoC FPGA It also comes with DC 3 3V VCC3P3 and tw...

Page 32: ...47 PIN_AH2 TMD0 IO 3 3 3V TMD0_IO4 PIN_251 PIN_AE8 TMD0 IO 4 3 3V TMD0_IO5 PIN_253 PIN_AF9 TMD0 IO 5 3 3V TMD0_IO6 PIN_257 PIN_AG5 TMD0 IO 6 3 3V TMD0_IO7 PIN_259 PIN_AH4 TMD0 IO 7 3 3V TMD1_IO0 PIN_240 PIN_AF11 TMD1 IO 0 3 3V TMD1_IO1 PIN_242 PIN_AF10 TMD1 IO 1 3 3V TMD1_IO2 PIN_246 PIN_AE12 TMD1 IO 2 3 3V TMD1_IO3 PIN_248 PIN_AD12 TMD1 IO 3 3 3V TMD1_IO4 PIN_252 PIN_AD10 TMD1 IO 4 3 3V TMD1_IO5 ...

Page 33: ...in Figure 5 6 Figure 5 6 Signals of the 2x5 Header These Analog inputs are shared with the Arduino s analog input pin ADC_IN0 ADC_IN5 Figure 5 7 shows the connections between the FPGA 2x5 header Arduino Analog input and the A D converter More information about the A D converter chip is available in its datasheet It can be found on manufacturer s website or in the directory Datasheet ADC of TSoM Ba...

Page 34: ...DMI folder on the Kit System CD Table 5 7 lists the HDMI Interface pin assignments and signal names relative to the Cyclone V SoC device Figure 5 8 Connections between the Cyclone V SoC FPGA and HDMI Transmitter Chip Table 5 7 HDMI Pin Assignments Schematic Signal Names and Functions Signal Name 260 pin Edge Connector Pin No FPGA Pin No Description I O Standard HDMI_TX_D0 PIN_221 PIN_AC4 Video Dat...

Page 35: ...3 V HDMI_TX_D21 PIN_194 PIN_T12 Video Data bus 3 3 V HDMI_TX_D22 PIN_198 PIN_T11 Video Data bus 3 3 V HDMI_TX_D23 PIN_200 PIN_U11 Video Data bus 3 3 V HDMI_TX_CLKPIN_203 PIN_AB26 Video Clock 3 3 V HDMI_TX_DE PIN_204 PIN_V12 Data Enable Signal for Digital Video 3 3 V HDMI_TX_HS PIN_215 PIN_Y5 Horizontal Synchronization 3 3 V HDMI_TX_VS PIN_217 PIN_Y4 Vertical Synchronization 3 3 V HDMI_TX_INT PIN_1...

Page 36: ...deo design audio design and I2C design A set of built in video patterns and audio serial data will be sent to the HDMI transmitter to drive the HDMI display with speaker Users can hear the beeping sound from the speaker when SW0 is set to 1 on the TSoM board The resolution can be switched by pressing KEY1 System Block Diagram Figure 6 1 shows the system block diagram of this reference design The H...

Page 37: ...at is 24 bit RGB 4 4 4 For more details please refer to the document ADV7513_Programming_Guide_R0 pdf Audio Generator The ADV7513 can accommodate 2 to 8 channels of I2S audio at up to a 192 KHz sampling rate The ADV7513 supports I2S standard left justified serial audio and right justified serial audio Figure 6 2 shows the left justified serial audio with I2S standard audio of 16 bit per channel Fi...

Page 38: ...tterns The module Video Source Selector controls the selection of current video timing among built in display modes listed in Table 6 2 The module Mode Control allows users to switch current display mode alternatively via KEY1 Table 6 2 Built in display modes for the HDMI TX demonstration Demonstration File Locations Hardware project directory HDMI_TX Bitstream used DE10_Nano_HDMI_TX sof Demo batc...

Page 39: ...nitor to be powered up There will be a pre defined video pattern shown on the monitor as shown in Figure 6 4 The SW0 is used to enable disable the sound output on the TSoM board When you switch the SW0 button to an upper position you will hear a beep sound from the speaker of the HDMI display Figure 6 4 The video pattern in the HDMI TX demonstration 6 6 2 2 D DD DR R3 3_ _R RT TL L This demonstrat...

Page 40: ...mory Figure 6 5 Block Diagram of the DDR3_RTL Demonstration Intel DDR3 SDRAM Controller with UniPHY To use intel DDR3 controller please perform the three major steps below 1 Create correct pin assignments for DDR3 2 Setup correct parameters in the dialog of DDR3 controller Design Tools Quartus Prime v17 1 Demonstration Source Code Project Directory Demonstration FPGA DDR3 Bit Stream DDR3 output_fi...

Page 41: ...ster II driver if necessary Power on the TSoM evaluation kit Execute the demo batch file test bat under the batch file folder DDR3 demo_batch Press KEY0 on TSoM evaluation kit to start the verification process After approximately 1 seconds LED0 stay on to indicate the DDR3 have passed the test Table 6 3 lists the LED indicators If LED1 is not blinking it means the 50MHz clock source is not working...

Page 42: ...rted from a user specified SRAM object file sof in Quartus The sof file is generated after the project compilation is successful The steps of converting sof to jic in Quartus II are listed below Before Programming Begins The FPGA should be set to AS x1 mode i e MSEL 4 0 10010 to use the EPCS as a FPGA configuration device Note that the factory default mode is FPPx32 mode MSEL 4 0 01010 User can se...

Page 43: ...gn file into the EPCS device a jic file is required Here s how to convert the sof file generated by Quartus compile to jic 1 Choose Convert Programming Files from the File menu of Quartus II 2 Select JTAG Indirect Configuration File jic from the Programming file type field in the dialog of Convert Programming Files ...

Page 44: ...device field 4 Choose Active Serial from the Mode filed 5 Browse to the target directory from the File name field and specify the name of output file 6 Click on the SOF data in the section of Input files to convert 7 Click Add File 8 Select the sof to be converted to a jic file from the Open File dialog ...

Page 45: ...TSoM Evaluation Kit User Manual 44 www terasic com July 26 2019 9 Click Open and the Convert Programming Files page will appear ...

Page 46: ...valuation Kit User Manual 45 www terasic com July 26 2019 10 Click on the Flash Loader and click Add Device 11 The Select Devices page will appear please select the targeted FPGA to be programed into the EPCS ...

Page 47: ...TSoM Evaluation Kit User Manual 46 www terasic com July 26 2019 12 Click OK and the Convert Programming Files page will appear ...

Page 48: ...e jic file is generated Write JIC File into the EPCS Device 1 Make sure the MSEL 4 0 is set to 10010 in AS mode 2 Choose Programmer from the Tools menu and the Chain cdf window will appear 3 Click Auto Detect and then select the correct device 5CSEBA6 Both FPGA device and HPS should be detected ...

Page 49: ...com July 26 2019 4 Double click the red rectangle region shown in below and the Select New Programming File page will appear Select the jic file to be programmed 5 Program the EPCS device by clicking the corresponding Program Configure box A factory ...

Page 50: ...TSoM Evaluation Kit User Manual 49 www terasic com July 26 2019 default SFL image will be loaded 6 Click Start to program the EPCS device ...

Page 51: ...4 0 is set to 10010 in AS mode 3 Choose Programmer from the Tools menu and the Chain cdf window will appear 4 Click Auto Detect and then select correct device both FPGA device and HPS will detected 5 Double click the red rectangle region shown in below and the Select New Programming File page will appear Select the correct jic file ...

Page 52: ...TSoM Evaluation Kit User Manual 51 www terasic com July 26 2019 6 Erase the EPCS device by clicking the corresponding Erase box A factory default SFL image will be loaded ...

Page 53: ...TSoM Evaluation Kit User Manual 52 www terasic com July 26 2019 7 Click Start to erase the EPCS device ...

Page 54: ...rm the link below and use the tool such as Win32 Disk Imager to write the linux image file tsom_linux_console zip into the Mircro SD card http mail terasic com tw johnny release tsom tsom_linux_console zip 3 Download the eMMC image file from the link below and extract it then copy the image file tsom_emmc_168M img to the fat partition of sdcard http mail terasic com tw johnny release tsom tsom_emm...

Page 55: ...is switch to the ON position which represents the HPS boot from the SD Card 7 Connect the PC and TSoM evaluation kit via mini USB cable and connect the Power adapter to power on the board 8 Use the terminal emulation program such as Putty on the operating system to connect to Linux running on TSoM ...

Page 56: ...ion Kit User Manual 55 www terasic com July 26 2019 9 Press the CPU KEY1 WARM_RST button on the TSoM module and wait for the Hit any key to stop autoboot 5 to appear in the Putty window Press any key to enter uboot ...

Page 57: ...uly 26 2019 10 Enter the command fatls mmc 0 1 to view the contents of the sdcard fat partition 11 Enter the command fatload mmc 0 1 loadaddr tsom_emmc_168M img to load the img file into the DDR3 12 Switch SW1 to OFF position to switch to eMMC boot mode ...

Page 58: ...Evaluation Kit User Manual 57 www terasic com July 26 2019 13 Enter the command mmc rescan to rescan the eMMC device 14 Enter the command mmc write loadaddr 0 0x510e0 to program image file to the eMMC device ...

Page 59: ...t is block each block has 512 bytes size The size of the image file here is 169984000 bytes i e 169984000 512 332000 block 332000 converted to hexadecimal is 0x510e0 16 Press the COLD_RST button of the TSoM evaluation kit to reboot the board into linux When the login in message appears that shows the programming eMMC success ...

Page 60: ...After the linux is boot enter root to login the system then mount the USB flash drive and eMMC memory s partition one to linux Commands mount dev sda1 mnt card and mount dev mmcblk0p1 mnt ram sda is USB flash drive mmcblk0p1 is emmc memory s partition one ignore the information when you do mount 5 Copy your new files from the USB flash drive to the eMMC memory with commands cp mnt card zImage mnt ...

Page 61: ...TSoM Evaluation Kit User Manual 60 www terasic com July 26 2019 7 Press the COLD_RST button to reboot TSoM board then it will boot linux with your new updated files ...

Page 62: ...ww terasic com July 26 2019 Appendix 9 9 1 1 R Re ev vi is si io on n H Hi is st to or ry y Version Change Log V1 0 Initial Version Preliminary V1 1 Modify ch3 ch7 and ch8 according rev B version Copyright Terasic Inc All rights reserved ...

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