Terasic TSOM, Manual

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TSoM Evaluation
Kit User Manual 29
www.terasic.com
July 26, 2019
connected directly and individually to the FPGA. When the switch is set to the DOWN position
(towards the edge of the board), it generates a low logic level to the FPGA. When the switch is
set to the UP position, a high logic level is generated to the FPGA.
Figure 5-3 Connections between the slide switches and the Cyclone V SoC FPGA
There are also two user-controllable LEDs connected to the FPGA. Each LED is driven directly
and individually by the Cyclone V SoC FPGA; driving its associated pin to a high logic level or
low level to turn the LED on or off, respectively.
Figure 5-4 shows the connections between
LEDs and Cyclone V SoC FPGA. Table 5-1 , Table 5-2 and Table 5-3 list the pin assignment of
user push-buttons, switches, and LEDs.
Figure 5-4 Connections between the LEDs and the Cyclone V SoC FPGA