TSoM Evaluation
Kit User Manual
12
www.terasic.com
July 26, 2019
configuration bit stream is downloaded directly into the Cyclone V SoC FPGA. The FPGA will
retain its current status as long as the power keeps applying to the board; the configuration
information will be lost when the power is off.
2.
AS programming
: The other programming method is Active Serial configuration. The
configuration bit stream is downloaded into the serial configuration device (EPCS64), which
provides non-volatile storage for the bit stream. The information is retained within EPCS64
even if the TSoM evaluation kit board is turned off. When the board is powered on, the
configuration data in the EPCS64 device is automatically loaded into the Cyclone V SoC
FPGA.
JTAG Chain on TSoM Evaluation Kit
The FPGA device can be configured through JTAG interface on TSoM evaluation kit board, but the
JTAG chain must form a closed loop, which allows Quartus II programmer to the detect FPGA
device.
Figure 3-6
illustrates the JTAG chain on TSoM evaluation kit board.
In addition, the TSoM evaluation kit has one external JTAG Header (J7) reserved for users to
connect to JTAG chain of the TSoM evaluation kit via external blaster. The J7 header is not
installed, so users need to solder a 2.54mm 2 x 5 male pin header if it is necessary.
Figure 3-6 Path of the JTAG chain
Configure the FPGA in JTAG Mode
There are two devices (FPGA and HPS) on the JTAG chain. The following shows how the FPGA is
programmed in JTAG mode step by step.
Open the Quartus II programmer, please Choose
Tools
>
Programmer
. The Programmer window
opens. Please click “
Hardware Setup
”, as circled in
Figure 3-7
.
Summary of Contents for TSOM
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