WE866 HW User Guide
1VV0301330 Rev. 3
Page
24
of
54
2018-03-13
Low power deep sleep
The low power deep sleep (LPDS) mode is an energy-efficient and transparent sleep mode
that is entered automatically during periods of inactivity based on internal power
optimization algorithms. The device can wake up in less than 3ms from the internal timer or
from any incoming host command. Typical battery drain in this mode is 115µA. During LPDS
mode, the device retains the software state and certain configuration information. The
operation is transparent to the external host; thus, no additional handshake is required to
enter or exit this sleep mode.
Hibernate
The hibernate mode is the lowest power mode in which all of digital logic is power-gated.
Only a small section of the logic powered directly by the main input supply is retained. The
RTC is kept running and the device wakes up once the nHIB line is asserted by the host
device. Ultralow leakage when disabled (hibernate mode) with a current of less than 4 μA
with the RTC running. The average wake-up time is longer than LPDS mode, is about 50ms.
ITEM
NAME
DESCRIPTION
MIN
TYP MAX
THib
min
Minumum
hibernate time
Minimum pulse width of nHIB
being low
10ms
T
wakeup_Hib
Hardware wakeup
time plus firmware
initialization time
(1)
50ms
(1) If temperature changes by more than 20°C, initialization time from HIB can increase
by 200ms due to radio calibration.
Shutdown
The shutdown mode is the lowest power-mode system-wise. All device logics are off,
including the real.time clock (RTC). The wake-up time in this mode is longer than hibernate,
is about 1.1s.
Summary of Contents for WE866
Page 1: ...04 2016 Mod 0805 2016 08 Rev 5 WE866 HW User Guide 1VV0301330 Rev 3 2018 03 13 13...
Page 10: ...WE866 HW User Guide 1VV0301330 Rev 3 Page 10 of 54 2018 03 13 Related Documents...
Page 33: ...WE866 HW User Guide 1VV0301330 Rev 3 Page 33 of 54 2018 03 13 7 MECHANICAL DESIGN Drawing...
Page 54: ...04 2016 Mod 0805 2016 08 Rev 5...
