Teledyne SP Devices ADQ8-8C, Manual

Page: 2 / 50

17-2000 C
2020-09-17
2(50)
ADQ8-8C Manual
17-2000 C 2020-09-17
2(50)
Table of content
1 INTRODUCTION ........................................................................................................... 5
1.1 ADQ8-8C Architecture ................................................................................................... 5
1.2 Fundamental design properties ..................................................................................... 5
1.2.1 Data format .................................................................................................................................. 5
1.2.2 Calibration.................................................................................................................................... 6
1.2.3 Data acquisition nomenclature .................................................................................................... 6
1.2.4 Sampling clock frequency............................................................................................................ 6
1.2.5 System clocks.............................................................................................................................. 6
1.2.6 Analog signal range ..................................................................................................................... 7
1.3 Digitizer Studio overview................................................................................................ 8
2 SETTING UP THE ANALOG FRONT-END ................................................................... 9
2.1 ADQ8-8C AFE block diagram ........................................................................................ 9
2.2 Set input impedance ...................................................................................................... 9
2.3 Set analog input range................................................................................................... 9
2.4 Set analog DC-offset.................................................................................................... 10
2.5 Adjusting the digital gain and offset ............................................................................. 10
3 SIGNAL QUALITY ENHANCEMENT........................................................................... 11
3.1 Digital Baseline Stabilizer ............................................................................................ 11
4 TRIGGER..................................................................................................................... 12
4.1 Trigger block diagram .................................................................................................. 12
4.2 Introduction .................................................................................................................. 13
4.3 Position of the trigger in the data ................................................................................. 13
4.4 Timestamp ................................................................................................................... 14
4.4.1 Timestamp definitions................................................................................................................ 14
4.4.2 Timestamp reset ........................................................................................................................ 14
4.5 Blocking triggers for synchronization ........................................................................... 16
4.5.1 Function overview...................................................................................................................... 16
4.5.2 Block triggers once .................................................................................................................... 18
4.5.3 Windowing triggers .................................................................................................................... 18
4.5.4 Gating and windowing triggers .................................................................................................. 18
4.5.5 Programming sequence for using trigger blocking .................................................................... 18
4.6 Trigger jitter.................................................................................................................. 19
4.6.1 Trigger jitter definitions .............................................................................................................. 19
4.6.2 Asynchronous triggering ............................................................................................................ 19
4.6.3 Synchronous trigger................................................................................................................... 20
4.6.4 Extended trigger resolution........................................................................................................ 20
4.7 Software trigger............................................................................................................ 20
4.8 External Trigger Inputs................................................................................................. 21
4.8.1 External trigger TRIG front panel connector .............................................................................. 21
4.8.2 External trigger SYNC connector............................................................................................... 22
4.8.3 Driving the external TRIG/SYNC signal by controlling input impedance ................................... 22
4.9 External trigger in the backplane ................................................................................. 23
4.9.1 PXIe interface ............................................................................................................................ 23
4.9.2 MTCA.4 interface....................................................................................................................... 24
4.10 Level trigger ................................................................................................................. 25
4.10.1Setting the level trigger level...................................................................................................... 26
4.10.2Level trigger and DBS................................................................................................................ 26
4.10.3Controlling noise sensitivity ....................................................................................................... 26
4.11 Internal trigger.............................................................................................................. 27