Teledyne SP Devices ADQ8-8C, Manual

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17-2000 C
2020-09-17
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ADQ8-8C Manual
17-2000 C 2020-09-17
15(50)
1. The timestamp counter is reset at power-up. This methods does not, however, have absolute preci-
sion, since the timing of the power up is not defined. In a multi-board system, the timestamp will dif-
fer between the boards.
2. With a software reference reset the user has full control of the reset procedure. A reference time
point is created in the users application, which is used for aligning time-stamps in different units.
After power-up the user runs a custom timestamp reset sequence including:
• Apply a reference signal to all boards.
• Trigger a record on the reference signal.
• Read the time-stamps from the records and call this reference;
TIME_STAMP_REFERENCE .
• Start the experiment and subtract the timing reference from each record as
TIME_STAMP
=
TIME_STAMP_OF_RECORD
–
TIME_STAMP_REFERENCE
.
3. The third method is to apply an external trigger to reset the timestamp reset, Figure 7 . This method
has the possibility to synchronize several boards to full precision of the external trigger. See Sec-
tion 4.5 . The sequence of operation is:
• DisarmTimestampSync
• SetupTimestampSync
• ArmTimestampSync
The number of reset pulses are counted and the information is stored in the record header, Section
7.9 . However, if there are no triggers accepted, there will be no record headers available. To verify
that there is activity going on, the number of reset pulses can also be read from a register via
GetTriggerBlockingGateCount
.
4. The fourth method is to reset the timestamp with the sync signal, Figure 7 . The difference between
using the external trigger and the sync is that the external trigger has the a sample resolution while
the sync timing resolution is controlled by the Data Clock in the FPGA. Note that the backplane trig-
gers in –PXIe and –MTCA formats work in the same way as the sync signal.